View DS26303LN-75_3419159.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 97 rev 072205 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds26303 is an 8-channel short-haul line interface unit (liu) that supports e1/t1/j1 from a single 3.3v power supply. a wide variety of applications are supported through internal termination or external termination. a single bill of material can support e1/t1/j1 with minimum external components. redundancy is supported through nonintrusive monitoring, optimal high-impedance modes, and configurable 1:1 or 1+1 backup enhancements. an on-chip synthesizer generates the e1/t1/j1 clock rates by a single master clock input of various frequencies. two clock output references are also offered. applications t1 digital cross-connects atm and frame relay equipment wireless base stations isdn primary rate interface e1/t1/j1 multiplexer and channel banks e1/t1/j1 lan/wan routers functional diagram tneg rclk tpos tclk rpos rneg software control, hardware control and jtag transmitter receiver rlos 1 8 rtip rring modesel jtag tttip tring features 8 complete e1, t1, or j1 short haul line interface units independent e1, t1, or j1 selections internal software-selectable transmit and receive-side termination crystal-less jitter attenuator selectable single-rail and dual-rail mode and ami or hdb3/ b8zs line encoding and decoding detection and generation of ais digital/analog loss-of-signal detection as per t1.231, g.775, and etsi 300233 external master clock can be multiple of 2.048mhz or 1.544mhz for t1/j1 or e1 operation; this clock will be internally adapted for t1 or e1 use built-in bert tester for diagnostics 8-bit parallel interface support for intel or motorola mode or a 4-wire serial interface hardware mode interface support transmit short-circuit protection g.772 nonintrusive monitoring specification compliance to the latest t1 and e1 standards?ansi t1.102, at&t pub 62411, t1.231, t1.403, itu g.703, g.742, g.775, g.823, etsi 300 166, and etsi 300 233 single 3.3v supply with 5v tolerant i/o jtag boundary scan as per ieee 1149.1 160-pin pbga/144-pin elqfp package ordering information part temp range pin-package ds26303g-xxx* 0c to +70c 160 pbga ds26303gn-xxx* -40c to +85c 160 pbga ds26303l-xxx 0c to +70c 144 elqfp ds26303l-xxx+ 0c to +70c 144 elqfp ds26303ln-xxx -40c to +85c 144 elqfp ds26303ln-xxx+ -40c to +85c 144 elqfp note: when xxx is 075, the part defaults to 75 impedance in e1 mode; when xxx is 120, the part defaults to 120 impedance. + denotes a lead-free/rohs-compliant device. * future product?contact factory for availability. ds26303 3.3v, e1/t1/j1, short-haul, octal line interface unit www.maxim-ic.com ds26303
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 2 of 97 table of contents 1 detailed description ........................................................................................................... .6 2 telecom specification s compli ance............................................................................... 7 3 block diagrams ................................................................................................................. ..... 9 4 pin description ................................................................................................................ ...... 11 4.1 h ardware and h ost p ort o peration .................................................................................... 21 4.1.1 hardware mode.................................................................................................................. ................. 21 4.1.2 serial port operation .......................................................................................................... ................ 22 4.1.3 parallel port operation........................................................................................................ ................ 23 4.1.4 interrupt handling............................................................................................................. ................... 23 5 registers...................................................................................................................... ........... 25 5.1 r egister d escription ............................................................................................................. 30 5.1.1 primary registers.............................................................................................................. .................. 30 5.1.2 secondary registers............................................................................................................ ............... 38 5.1.3 individual liu registers ....................................................................................................... ............... 39 5.1.4 bert registers ................................................................................................................. ................. 46 6 functional description ..................................................................................................... 53 6.1 p ower -u p and r eset .............................................................................................................. 53 6.2 m aster c lock ......................................................................................................................... 53 6.3 t ransmitter ............................................................................................................................ 54 6.3.1 transmit line templates ........................................................................................................ ............ 55 6.3.2 liu transmit front end......................................................................................................... .............. 57 6.3.3 dual-rail mode ................................................................................................................. .................. 58 6.3.4 single-rail mode............................................................................................................... .................. 58 6.3.5 zero suppression?b8zs or hdb3 .................................................................................................. .. 58 6.3.6 transmit power-down ............................................................................................................ ............ 58 6.3.7 transmit all ones.............................................................................................................. .................. 58 6.3.8 drive failure monitor.......................................................................................................... ................. 58 6.4 r eceiver ............................................................................................................................... ... 58 6.4.1 peak detector and s licer ....................................................................................................... ............. 58 6.4.2 clock and data recovery ........................................................................................................ ........... 59 6.4.3 loss of signal................................................................................................................. ..................... 59 6.4.4 ais ............................................................................................................................ .......................... 60 6.4.5 bipolar violation and excessive zero detector.................................................................................. .61 6.4.6 liu receiver front end ......................................................................................................... ............. 61 6.5 h itless -p rotection s witching (hps).................................................................................... 61 6.6 j itter a ttenuator .................................................................................................................. 63 6.7 g.772 m onitor ........................................................................................................................ 64 6.8 l oopbacks ............................................................................................................................... 64 6.8.1 analog loopback ................................................................................................................ ................ 64 6.8.2 digital lo opback............................................................................................................... ................... 64 6.8.3 remote loopback ................................................................................................................ ............... 65 6.9 bert........................................................................................................................... ............. 66 6.9.1 configuration and monitoring................................................................................................... ........... 66 6.9.2 receive pattern detection ...................................................................................................... ............ 67 6.9.3 transmit pattern generation.................................................................................................... ........... 68 6.10 s pecial t est f unctions .......................................................................................................... 69 6.10.1 metal options .................................................................................................................. .................... 69 7 jtag boundary scan architect ure and test access po rt.................................. 70 7.1 tap c ontroller s tate m achine ............................................................................................ 71 7.2 i nstruction r egister ............................................................................................................. 74 7.3 t est r egisters ....................................................................................................................... 75 7.3.1 boundary scan register ......................................................................................................... ............ 75
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 3 of 97 7.3.2 bypass register ................................................................................................................ .................. 75 7.3.3 identificati on register ........................................................................................................ ................. 75 8 operating parameters....................................................................................................... 76 9 thermal characteristics ................................................................................................. 77 10 ac characteristics ............................................................................................................. 78 10.1 l ine i nterface c haracteristics ............................................................................................ 78 10.2 p arallel h ost i nterface t iming c haracteristics ............................................................... 79 10.3 s erial p ort ............................................................................................................................. 91 10.4 s ystem t iming ......................................................................................................................... 92 10.5 jtag t iming ............................................................................................................................ 94 11 package information.......................................................................................................... 95 11.1 e lqfp p ackage o utline (1 of 2)............................................................................................ 95 11.2 e lqfp p ackage o utline (2 of 2)............................................................................................ 96 12 document revision history .............................................................................................. 97
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 4 of 97 list of figures figure 3-1. block diagram ...................................................................................................... ..................................... 9 figure 3-2. receive logic detail............................................................................................... ................................. 10 figure 3-3. trans mit logic detail.............................................................................................. ................................. 10 figure 4-1. 160-pin pbga pin assignment........................................................................................ ....................... 19 figure 4-2. 144-pin elqfp pin assignment ....................................................................................... ...................... 20 figure 4-3. serial port operation for write access ............................................................................. ...................... 22 figure 4-4. serial port operatio n for read access with clke = 0 ................................................................ ........... 22 figure 4-5. serial port operatio n for read access with clke = 1 ................................................................ ........... 23 figure 4-6. interrupt handling flow diagram .................................................................................... ........................ 24 figure 6-1. pre-scaler pll and clock generator................................................................................. ..................... 53 figure 6-2. t1 transmit pulse templates ........................................................................................ ......................... 55 figure 6-3 e1 transmit pulse templates ......................................................................................... ......................... 56 figure 6-4. liu front end ...................................................................................................... .................................... 57 figure 6-5. hps logic .......................................................................................................... ..................................... 62 figure 6-6. hps block diagram.................................................................................................. ............................... 62 figure 6-7. jitter attenuation ................................................................................................. .................................... 63 figure 6-8. analog loopback.................................................................................................... ................................. 64 figure 6-9. digital loopback................................................................................................... ................................... 65 figure 6-10. remote loopback ................................................................................................... .............................. 65 figure 6-11. prbs synchronization state diagram................................................................................ .................. 67 figure 6-12. repetitive pattern synchronization state diagram .................................................................. ............. 68 figure 7-1. jtag func tional block diagram ...................................................................................... ....................... 70 figure 7-2. tap contro ller state diagram....................................................................................... .......................... 73 figure 10-1. intel nonmuxed read cycle ......................................................................................... ........................ 80 figure 10-2. intel mux read cycle .............................................................................................. .............................. 81 figure 10-3. intel nonmux write cycle.......................................................................................... ............................ 83 figure 10-4. intel mux write cycle ............................................................................................. ............................... 84 figure 10-5. motorola nonmux read cycle ........................................................................................ ...................... 86 figure 10-6. motorola mux read cycle ........................................................................................... .......................... 87 figure 10-7. motorola nonmux write cycle ....................................................................................... ....................... 89 figure 10-8. motorola mux write cycle .......................................................................................... ........................... 90 figure 10-9. serial bus timing write operation................................................................................. ....................... 91 figure 10-10. serial bus timing r ead operation with clke = 0................................................................... ........... 91 figure 10-11. serial bus timing r ead operation with clke = 1................................................................... ........... 91 figure 10-12. transmitter systems timing ....................................................................................... ........................ 92 figure 10-13. receiver systems timing .......................................................................................... ......................... 93 figure 10-14. jtag timing ...................................................................................................... ................................. 94
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 5 of 97 list of tables table 2-1. t1-related teleco mmunications sp ecificat ions ........................................................................ ................ 7 table 2-2. e1-related teleco mmunications sp ecificat ions ........................................................................ ................ 8 table 4-1. pin descriptions.................................................................................................... .................................... 11 table 4-2. hardware mode configuratio n examples................................................................................ ................. 21 table 4-3. parallel port mo de selection and pin functions ...................................................................... ................ 23 table 5-1. primary register set ................................................................................................ ................................ 25 table 5-2. secondar y register set.............................................................................................. .............................. 26 table 5-3. individual liu register set ......................................................................................... .............................. 26 table 5-4. bert register set ................................................................................................... ................................ 27 table 5-5. primary register set bit map ........................................................................................ ........................... 28 table 5-6. secondary r egister set bit map ...................................................................................... ........................ 28 table 5-7. individual liu register set bit map................................................................................. ......................... 28 table 5-8. bert register bit map ............................................................................................... ............................. 29 table 5-9. g.772 monitoring control ............................................................................................ ............................. 33 table 5-10. tst template select transmitter register ........................................................................... ................. 35 table 5-11. templa te selection................................................................................................. ................................ 36 table 5-12. address pointer bank selection..................................................................................... ........................ 37 table 5-13. mclk selections .................................................................................................... ................................ 41 table 5-14. pll clock select ................................................................................................... ................................. 44 table 5-15. cl ock a select ..................................................................................................... ................................... 44 table 6-1. telecommunications specificat ion compliance for ds26303 transmitters ............................................ 54 table 6-2. registers related to control of ds26303 transmitters ................................................................ ........... 54 table 6-3. ds26303 te mplate selections ......................................................................................... ........................ 55 table 6-4. liu front-end values ................................................................................................ ............................... 57 table 6-5. loss criteria t1.231, g. 775, and etsi 300 233 specific ations........................................................ ....... 59 table 6-6. ais criteria t1.231, g.7 75, and etsi 300 2 33 specific ations......................................................... ........ 60 table 6-7. ais detecti on and reset criteria .................................................................................... ......................... 60 table 6-8. registers related to ais detection.................................................................................. ........................ 60 table 6-9. bpv, code violation, and excessive zero error reporting ............................................................. ........ 61 table 6-10. pseudorando m pattern generation.................................................................................... .................... 66 table 6-11. repetitive pattern generation ...................................................................................... .......................... 66 table 7-1. instruction codes for ieee 1149.1 architecture...................................................................... ................. 74 table 7-2. id code structure................................................................................................... .................................. 75 table 7-3 device id codes...................................................................................................... .................................. 75 table 8-1. recommended dc operating conditions ................................................................................. ............... 76 table 8-2. capacitance......................................................................................................... ..................................... 76 table 8-3. dc characteristics.................................................................................................. .................................. 76 table 9-1. thermal characteristics............................................................................................. ............................... 77 table 10-1. transmitter characteristics ........................................................................................ ............................ 78 table 10-2. receiver characteristics........................................................................................... .............................. 78 table 10-3. intel read mode characteristics .................................................................................... ........................ 79 table 10-4. intel write cycle characteristics .................................................................................. .......................... 82 table 10-5. motorola read cycle characteristics ................................................................................ ..................... 85 table 10-6. motorola write cycle characteristics ............................................................................... ...................... 88 table 10-7. serial port timing characteristics ................................................................................. ......................... 91 table 10-8. transmitter system timing .......................................................................................... .......................... 92 table 10-9. receiver system timing............................................................................................. ............................ 93 table 10-10. jtag timing characteristics....................................................................................... ......................... 94
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 6 of 97 1 detailed description the ds26303 is a single-chip, 8-channel, short-haul line interface unit (liu) for t1 (1.544mbps) and e1 (2.048mbps) applications. eight independent receivers and transmitters are provided in a single pbga package or an elqfp package. the lius can be individually selected for t1, j1, or e1 operation. the liu requires a single reference clock called mclk. mclk can be either 1.544mhz or 2.048mhz or a multiple thereof, and either frequency can be internally adapted for t1, j1, or e1 mode. internal impedance match provided for both transmit and receive paths reduces external component count. the transmit waveforms are compliant to g.703 and t1.102 specification. the ds26303 provides software-selectable internal transmit termination for 100 t1 twisted pair, 110 j1 twisted pair, 120 e1 twisted pair, and 75 e1 coaxial applications. the transmitters have fast high- impedance capability and can be individually powered down. the receivers can function with up to 15db of receive signal attenuation for t1 mode and e1 mode. the ds26303 can be configured as a 7-channel liu with channel 1 used for nonintrusive monitoring in accordance with g.772. the receivers and transmitters can be programmed into single-rail or dual-rail mode. ami or hdb/b8zs encoding and decoding is selectable in single-rail mode. a 128-bit crystal-less on-board jitter attenuator for each liu can be placed in the receive or transmit directions. the jitter attenuator meets the etsi ctr12/13 itu g.736, g.742, g.823, and at&t pub6411 specifications. the ds26303 detects and generates ais in accordance with t1.231, g.775, and etsi 300233. loss of signal is detected in accordance with t1.231, g.775, and etsi 300233. the ds26303 can perform digital, analog, remote, and dual loopbacks on individual lius. jtag boundary scan is provided for the digital pins. the ds26303 can be configured using an 8-bit multiplexed or nonmultiplexed intel or motorola port, a 4-pin serial port, or in limited modes of operation using hardware mode. the analog ami/hdb3 waveform of the e1 line or the ami/b8zs waveform of the t1 line is transformer coupled into the rtip and rring pins of the ds26303. the user has the option to select internal termination of 75 , 100 , 110 , or 120 applications. the device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator, outputting the received line clock at rclk and data at rpos and rneg. the ds26303 receivers can recover data and clock for up 15db of attenuation of the transmitted signals in t1 and e1 mode. receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8 . the ds26303 contains eight identical transmitters. digital transmit data is input at tpos/tneg with reference to tclk. the data at these pins can be single rail or dual rail. this data is processed by waveshaping circuitry and line driver to output at ttip and tring in accordance with ansi t1.102 for t1/j1 or g.703 for e1 mask. the ds26303 drives the e1 or t1 line from the ttip and tring pins through a coupling transformer. the ds26303 functions with a 1:2 and 2:1 transformer for the tx and rx paths for operation, respectively.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 7 of 97 2 telecom specifications compliance the ds26303 liu meets all the relevant latest telecommunications specifications. the following table provides the t1 specifications and relevant sections that are applicable to the ds26303. table 2-1. t1-related telecommunications specifications ansi t1.102?digital hierarchy electrical interface ami coding b8zs substitution definition ds1 electrical interface. line rate 32ppm; pulse amplitude between 2.4v to 3.6 v peak; power level between 12.6dbm to 17.9dbm. the t1 pulse mask is provided that we comply. dsx-1 for cross connects the return loss is greater than 26db. the dsx-1 cable is restricted up to 655 feet. this specification also provides cable characteristics of dsx-cross connect cable?22 avg cable of 1000 feet. ansi t1.231?digital hierarchy?layer 1 in service performance monitoring bpv error definition, excessive zero definition, los description, ais definition ansi t1.403?network and customer installation interface?ds1 electrical interface description of the measurement of the t1 characteristics?100 , pulse shape and template according to t1.102; power level 12.4dbm to 19.7dbm when all ones are transmitted. lbo for the customer interface (ci) is specified as 0db, 7.5db, and 15db. line rate is 32ppm. pulse amplitude is 2.4v to 3.6 v. ais generation as unframed all ones is defined. the total cable attenuation is defined as 22db. the ds26303 functions up to 36db cable loss. note that the pulse mask defined by t1.403 and t1.102 are different?specifically at times 0.61, -0.27, -34, and 0.77. the ds26303 is compliant to both templates. pub 62411 this specification has tighter jitter tolerance and transfer characteristics than other specifications. the jitter transfer characteristics are tighter than g.736 and jitter tolerance is tighter the g.823.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 8 of 97 table 2-2. e1-related telecommunications specifications itut g.703 physical/electrical characteristics of g.703 hierarchical digital interfaces defines the 2048kbps bit rate: 2048 50ppm. the transmission media are 75 coax or 120 twisted pair; peak-to- peak space voltage is 0.237v; nominal pulse width is 244ns. return loss: 51hz to 102hz is 6db, 102hz to 3072hz is 8db, 2048hz to 3072hz is 14db nominal peak voltage is 2.37v for coax and 3v for twisted pair. the pulse mask for e1 is defined in g.703. itut g.736 characteristics of synchronous digita l multiplex equipment operating at 2048kbps the peak-to-peak jitter at 2048kbps must be less than 0.05ui at 20hz to 100hz. jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided. itut g.742 second-order digital multip lex equipment operating at 8448kbps the ds26303 jitter attenuator is compliant with jitter transfer curve for sinusoidal jitter input. itut g.772 this specification provides the method for using receiver for transceiver 0 as a monitor for the rest of the seven transmitter/receiver combinations. itut g.775 an los detection criterion is defined. itut g.823?the control of jitter and wander within digital networks that are based on 2.048kbps hierarchy g.823 provides the jitter amplitude tolerance at different frequencies, specifically 20hz, 2.4khz, 18khz, and 100khz. etsi 300 166 this specification provides transmit return loss of 6db for a range of 0.25fb to 0.05fb, and 8db for a range of 0.05fb to 1.5fb where fb equals 2.048khz for 2.048kbps interface. etsi 300 233 this specification provides los and ais signal criteria for e1 mode. pub 62411 this specification has tighter jitter tolerance and transfer characteristics than other specifications. the jitter transfer characteristics are tighter than g.736 and jitter tolerance is tighter then g.823.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 9 of 97 3 block diagrams figure 3-1. block diagram line drivers optional termination filter peak detector clock/data recovery analog loopback wave shaping remote loopback (dual mode) local loopback jitter attenuator remote loopback receive logic transmit logic vco/pll jitter attenuator mux 2.048mhz to 1.544mhz pll mux unframed all ones insertion rring rtip tring ttip t1clk e1clk rpos/rdat rneg/cv rclk tpos/tdat tneg tclk master clock adapter jtag port control and interrupt port interface clke rdb/rwb rdy/ackb/sdo motel asb/ale/sclk d7/ad7/ bswb a0 to a4 d0 to d6/ ad0 to ad6 csb intb jtrstb jtms jtclk jtdi jtdo mclk t1clk e1clk 88 typical of all 8 channels oe modesel wrb/dsb/sdi 8 5 reset rlos reset mux ds26303
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 10 of 97 figure 3-2. receive logic detail b8zs/hdb3/ami decoder (g.703, t1.102) bpvs, code violatiions (t1.231, o.161) ais detector g.775, etsi 300233, t1.231 excessive zero detect t1.231 mux all ones insert (ais) nrz data bpv/cv/exz rpos rneg/cv rclk los en srms iaisel aisel mclk ezde lascs pos neg rclk cvdeb encode encv lcs code encode figure 3-3. transmit logic detail mux tpos/ tdata tneg/ bpv b8zs/hdb3/ami coder (g.703, t1.102) tclk bpv insert lcs code encode beir to remote loopback srms
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 11 of 97 4 pin description table 4-1. pin descriptions pin name elqfp pbga type function analog transmit and receive ttip1 45 n5 ttip2 52 l5 ttip3 57 l10 ttip4 64 n10 ttip5 117 b10 ttip6 124 d10 ttip7 129 d5 ttip8 136 b5 analog output transmit bipolar tip for channel 1 to 8. these pins are differential line-driver tip outputs. these pins can be high impedance if pin oe is low. if the corresponding clock tclkn is low for 64 mclks, where n is 1 to 8 for the eight transmitters. this puts the corresponding transmitter in a power-down mode. when 1 is set in the oeb .oeb bit, the associated pin is high impedance. the differential outputs of ttipn and tringn can provide internal matched impedance for e1 75 , e1 120 , t1 100 , or j1 110 . tring1 46 p5 tring2 51 m5 tring3 58 m10 tring4 63 p10 tring5 118 a10 tring6 123 c10 tring7 130 c5 tring8 135 a5 analog output transmit bipolar ring for channel 1 to 8. these pins are differential line-driver ring outputs. these pins can be high impedance if pin oe is low. if the corresponding clock tclkn is low for 64 mclks, where n is 1 to 8 for the eight transmitters. this puts the corresponding transmitter in a power-down mode. when 1 is set in the oeb.oeb bit, the associated pin is high impedance. the differential outputs of ttipn and tringn can provide internal matched impedance for e1 75 , e1 120 , t1 100 , or j1 110 . rtip1 48 p7 rtip2 55 m7 rtip3 60 m8 rtip4 67 p8 rtip5 120 a8 rtip6 127 c8 rtip7 132 c7 rtip8 139 a7 analog input receive bipolar tip for channel 1 to 8. receive analog input for differential receiver. data and clock are recovered and output at rpos/rneg and rclk pins, respectively. the differential inputs of rtipn and rringn can provide internal matched impedance for e1 75 , e1 120 , t1 100 , or j1 110 . rring1 49 n7 rring2 54 l7 rring3 61 l8 rring4 66 n8 rring5 121 b8 rring6 126 d8 rring7 133 d7 rring8 138 b7 analog input receive bipolar ring for channel 1 to 8. receive analog input for differential receiver. data and clock are recovered and output at rpos/rneg and rclk pins, respectively. the differential inputs of rtipn and rringn can provide internal matched impedance for e1 75 , e1 120 , t1 100 , or j1 110 .
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 12 of 97 pin name elqfp pbga type function digital tx/rx tpos1/tdata1 37 n2 tpos2/tdata2 30 l2 tpos3/tdata3 80 l13 tpos4/tdata4 73 n13 tpos5/tdata5 108 b13 tpos6/tdata6 101 d13 tpos7/tdata7 8 d2 tpos8/tdata8 1 b2 i transmit positive-data input for channel 1 to 8/transmit data input for channel 1 to 8 tpos[1:8]: when the ds26303 is configured in dual-rail mode, the data input to tposn is output as a positive pulse on the line (tip and ring). tdata[1:8]: when the device is configured in single-rail mode, nrz data is input to tdatan. the data is encoded hdb3/b8zs or ami before being output to the line. tneg1 38 n3 tneg2 31 l3 tneg3 79 l12 tneg4 72 n12 tneg5 109 b12 tneg6 102 d12 tneg7 7 d3 tneg8 144 b3 i transmit negative data for channel 1 to 8. when the ds26303 is configured in dual-rail mode, the data input to tnegn is output as a negative mark on the line as follows: tposn tnegn output pulse 0 0 space 0 1 negative mark 1 0 positive mark 1 1 space when tnegn is pulled high for more than 16 consecutive tclk clock cycles, single-rail i/o is selected. tclk1 36 n1 tclk2 29 l1 tclk3 81 l14 tclk4 74 n14 tclk5 107 b14 tclk6 100 d14 tclk7 9 d1 tclk8 2 b1 i transmit clock for channel 1 to 8. the transmit clock must be 1.544mhz for t1 or 2.048mhz for e1 mode. tclkn is the clock used to sample the data tpos/tneg or tdat on the falling edge. the expected tclk can be inverted. if tclkn is high for 16 or more mclks, then transmit all-ones (tao) signals to the line side of the corresponding transmit channel. when tclkn starts clocking again, normal operation will begin again for the corresponding transmit channel. if tclkn is low for 64 or more mclks, the corresponding transmit channel on the line side powers down and must be put into high impedance. when tclkn starts clocking again the corresponding transmit channel powers up and comes out of high impedance. rpos1/rdata1 40 p2 rpos2/rdata2 33 m2 rpos3/rdata3 77 m13 rpos4/rdata4 70 p13 rpos5/rdata5 111 a13 rpos6/rdata6 104 c13 rpos7/rdata7 5 c2 rpos8/rdata8 142 a2 o, tri-state receive positive-data output for channel 1 to 8/receive data output for channel 1 to 8 rpos[1:8]: in dual-rail mode, the nrz data output indicates a positive pulse on rtip/rring. if a given receiver is in power- down mode, the associated rpos pin is high impedance. rdata[1:8] : in single-rail mode, nrz data is output to the pin. note: during an rlos condition, the rpos/rdata outputs remain active. rneg1/cv1 41 p3 rneg2/cv2 34 m3 rneg3/cv3 76 m12 rneg4/cv4 69 p12 rneg5/cv5 112 a12 o, tri-state receive negative-data output for channel 1 to 8/code violation for channel 1 to 8 rneg[1:8]: in dual-rail mode, the nrz data output indicates a negative pulse on rtip/rring. if a given receiver is in power- down mode, the associated rneg pin is high impedance. cv[1:8]: in single-rail mode, bipolar violation, code violation, and excessive zeros are reported by driving cvn high for one clock
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 13 of 97 pin name elqfp pbga type function rneg6/cv6 105 c12 rneg7/cv7 4 c3 rneg8/cv8 141 a3 excessive zeros are reported by driving cvn high for one clock cycle. if hdb3 or b8zs is not selected, this pin indicates only bpvs. note: during an rlos condition the output remains active. rclk1 39 p1 rclk2 32 m1 rclk3 78 m14 rclk4 71 p14 rclk5 110 a14 rclk6 103 c14 rclk7 6 c1 rclk8 143 a1 o, tri-state receive clock for channel 1 to 8. the receive data rpos/rneg or rdat is clocked out on the rising edge of rclk. rclk output can be inverted. if a given receiver is in power-down mode, the rclk is high impedance. mclk 10 e1 i master clock. this is an independent free-running clock that can be a multiple of 2.048mhz 50ppm for e1 mode or 1.544mhz 50ppm for t1 mode. the clock selection is available by mc bits mps0, mps1, freqs, and plle. a multiple of 2.048mhz can be internally adapted to 1.544mhz and a multiple of 1.544mhz can be internally adapted to 2.048mhz. in hardware mode, internal adaptation is not available so the user must provide 2.048mhz 50ppm for e1 mode or 1.544mhz 50ppm for t1 mode. rlos1/teclk 42 k4 o loss-of-signal output/t1-e1 clock rlos1: this output goes high when there is no transition on the received signal over a specified interval. the output goes low when there is sufficient ones density in the received signal. the rlos criteria for assertion and desertion criteria are described in the functional description section. the rlos outputs can be configured to comply with t1.231, itu g.775, or etsi 300 233. in hardware mode, etsi 300 233 ?rlos criteria? is not available. teclk: when enabled by register mc , this output becomes a t1- or e1-programmable clock output. for t1 or e1 frequency selection, see register ccr . this option is not available in hardware mode. rlos2/ rxprobea1 35 k3 rlos3/ rxprobeb1 75 k12 rlos4/ rxprobec1 68 k11 i/o loss-of-signal output/receive probe rlos[2:4]: see rlos1 pin description. rxprobe a1, b1, c1: used in test only. rlos5/ scan_do 113 e11 o loss-of-signal output/scan data output rlos5: see rlos1 pin description. scan_do: data output during scan. rlos6/ scan_di 106 e12 i/o loss-of-signal output/scan data input rlos6: see rlos1 pin description. scan_di: data input during scan. rlos7/ scan_clk 3 e3 i/o loss-of-signal output/scan clock rlos7: see rlos1 pin description. scan_clk: clock input during scan.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 14 of 97 pin name elqfp pbga type function rlos8/ scan_en 140 e4 i/o loss-of-signal output/scan enable rlos8: see rlos1 pin description. scan_en: enables scan during test when pin scan_mode is high. clka 93 g13 o, tri-state clock a. this output becomes a programmable clock output when enabled by register mc . for frequency options see register ccr . this option is not available in hardware mode. if this option is not used, the pin should be left unconnected. scan_mode 94 h13 i (pulled to v ss ) scan mode. selects scan mode when high. if not used, this pin should be left unconnected or grounded. hardware and port operation modesel 11 e2 i (pulled to v dd /2) mode selection. this pin is used to select the control mode of the ds26303. low hardware mode v dd /2 serial host mode high parallel host mode note: when left unconnected, do not route signals with fast transitions near modesel. this practice minimizes capacitive coupling. mux/ timprm 43 k2 i multiplexed/nonmultiplexed select pin/ transmit impedance/receive impedance match mux: in host mode with a parallel port, this pin is used to select multiplexed address and data operation or separate address and data. when mux is a high, multiplexed address and data is used. timprm: in hardware mode, this pin selects the internal transmit termination impedance and receive impedance match for e1 mode and t1/j1 mode. 0 75 for e1 mode or 100 for t1 mode 1 120 for e1 mode or 110 for j1 mode note: if the part number ends with 120, the default is 120 when low and 75 when high for el mode only. motel/ code 88 h12 i motorola intel select/code motel: when in parallel host mode, this pin selects motorola mode when low and intel mode when high. code: in hardware mode, ami encoding/decoding is selected when the pin is high for all the lius. when the pin is low, b8zs is selected for t1 mode and hdb3 for e1 mode for all the lius.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 15 of 97 pin name elqfp pbga type function csb/ jas 87 j11 i (in hw mode, pulled to v dd /2) chip select bar/jitter attenuator select csb: this signal must be low during all accesses to the registers. jas: in hardware mode, this pin is used as a jitter attenuator select. low jitter attenuator is in the transmit path. vddio/2 jitter attenuator is not used. high jitter attenuator is in the receive path. note: when left unconnected and in hardware mode, do not route signals with fast transitions near jas. this practice minimizes capacitive coupling. sclk/ale/ asb/ts2 86 j12 i shift clock/address latch enable/address strobe bar/template selection 2 sclk: in the serial host mode, this pin is the serial clock. data on sdi is clocked on the rising edge of sclk. the data is clocked on sdo on the rising edge of sclk if clke is high. if clke is low the data on sdo is clocked on the falling edge of sclk. ale: in parallel intel multiplexed mode, the address lines are latched on the falling edge of ale. tie ale pin high if using nonmultiplexed mode. asb: in parallel motorola multiplexed mode, the address is sampled on the falling edge of asb. tie asb pin high if using nonmultiplexed mode. ts2: in hardware mode, this pin signal is the most significant bit position in table 5-11 . rdb/rwb/ts1 85 j13 i read bar/read write bar/template selection 1 rdb: in intel host mode, this pin must be low for read operation. rwb: in motorola mode, this pin is low for write operation and high for read operation. ts1: in hardware mode, this pin signal is the second significant bit position in table 5-11 . sdi/wrb/dsb/ts0 84 j14 i serial data input/write bar/data strobe bar/template selection 0 sdi: in the serial host mode, this pin is the serial input sdi. it is sampled on the rising edge of sclk. wrb: in intel host mode, this pin is active low during write operation. the data or address (multiplexed mode) is sampled on the rising edge of wrb. dsb: in the parallel motorola mode, this pin is active low. during a write operation the data or address is sampled on the rising edge of dsb. during a read operation the data (d[7:0] or ad[7:0]) is driven on the rising edge of dsb. in the nonmultiplexed motorola mode, the address bus (a [5:0]) is latched on the falling edge of dsb. ts0: in hardware mode, this pin signal is the least significant bit position in table 5-11 .
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 16 of 97 pin name elqfp pbga type function sdo/rdy/ackb/ rimpoff 83 k14 i/o serial data out/ready output/acknowledge bar/receive impedance off sdo: in serial host mode, the sdo data is output on this pin. if a serial write is in progress this pin is in high impedance. during a read sdo is high impedance when the sdi is in command/ address mode. if clke is low, sdo is output on the rising edge of sclk, if clke is high on the falling edge. rdy: a low on this pin reports to the host that the cycle is not complete and wait states must be inserted. a high means the cycle is complete. ackb: in motorola parallel mode, a low on this pin indicates that the read data is available for the host or that the written data cycle is complete. rimpoff: in hardware mode when this pin is high, all the rtip and ring pins have internal impedance switched off. intb 82 k13 o, open drain active-low interrupt bar. this interrupt signal is driven low when an event is detected on any of the enabled interrupt sources in any of the register banks. when there are no active and enabled interrupt sources, the pin can be programmed to either drive high or not drive high. the reset default is to not drive high when there are no active enabled interrupt sources. all interrupt sources are disabled after a software reset and they must be programmed to be enabled. d7/ad7/bswp/lp8 28 k1 d6/ad6/lp7 27 j1 d5/ad5/lp6 26 j2 d4/ad4/lp5 25 j3 d3/ad3/lp4 24 j4 d2/ad2/lp3 23 h2 d1/ad1/lp2 22 h3 d0/ad0/lp1 21 g2 i/o (in hw mode, pulled to v dd / 2) data bus 7?0/address/data bus 7?0/bit swap/ loopback select 7?0 d[7:0]: in nonmultiplexed host mode, these pins are the bidirectional data bus. ad[7:0]: in multiplexed host mode, these pins are the bidirectional address/data bus. note that ad7 and ad6 do not carry address information, and in serial host mode ad6?ad0 should be grounded. bswp: in serial host mode, this pin defines the serial data position to be lsb first when low and msb first when high. lp[8:1] in hardware mode, these pins set the loopback modes for the corresponding liu as follows: low remote loopback v ddio / 2 no loopback high analog loopback note: when left unconnected and in hardware mode, do not route signals with fast transitions near lp1?lp8. this practice minimizes capacitive coupling.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 17 of 97 pin name elqfp pbga type function a4/rimpmsb 12 f4 a3/gmc3 13 f3 a2/gmc2 14 f2 a1/gmc1 15 f1 a0/gmc0 16 g3 i address bus 4?0/g.772 monitoring control/rx impedance mode select a[4:0]: these five pins are address pins in parallel host mode. in serial host mode and multiplexed host mode, these pins should be grounded. rimpmsb: in hardware mode when this pin is low, the internal impedance mode is selected, so rtip and ring require no external resistance component. when high, external impedance mode is selected so rtip and ring require external resistance. gmc[3:0]: in hardware mode, these signal pins are used to select transmitter or receiver for nonintrusive monitoring. receiver 1 is used to monitor channels 2 to 8 of one receiver from rtip2? rtip8/rring2?rring8 or one transmitter from ttip2? ttip8/tring2?tring8. these signal pins correspond to the bits in table 5-9 . oe 114 e14 i output enable. if this pin is pulled low, all the transmitter outputs (ttip and tring) are high impedance. additionally, the user may use this same pin to turn off all the impedance matching for the receivers at the same time if register bit gmr.rhpmc is set. clke 115 e13 i clock edge. when clke is high, sdo is valid on the falling edge of sclk. when clke is low sdo is valid on the rising edge of sclk. when clke is high, the rclk for all the channels is inverted. this aligns rpos/rneg on the falling edge of rclk and overrides the settings in register rclki . when low, rpos/rneg is aligned on the settings in register rclki . jtag jtrstb 95 g12 i, pullup jtag test port reset. this pin if low resets the jtag port. if not used it can be left floating. jtms 96 f11 i, pullup jtag test mode select. this pin is clocked on the rising edge of jtclk and is used to control the jtag selection between scan and test machine control. jtclk 97 f14 i jtag test clock. the data jtdi and jtms are clocked on rising edge of jtclk and jtdo is clocked out on the falling edge of jtclk. jtdo 98 f13 o, high-z jtag test data out. this is the serial output of the jtag port. the data is clocked out on the falling edge of jtclk. jtdi 99 f12 i, pullup test data input. this pin input is the serial data of the jtag test. the data on jtdi is clocked on the rising edge of jtclk. this pin can be left unconnected. power supplies dvdd 19 h1 ? 3.3v digital power supply dvss 20 h4 ? digital ground vddio 17, 92 g1, g14 ? 3.3v i/o power supply vssio 18, 91 g4, g11 ? i/o ground
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 18 of 97 pin name elqfp pbga type function tvdd1 44 n4, p4 tvdd2 53 l4, m4 tvdd3 56 l11, m11 tvdd4 65 n11, p11 tvdd5 116 a11, b11 tvdd6 125 c11, d11 tvdd7 128 c4, d4 tvdd8 137 a4, b4 ? 3.3v power supply for the transmitter. all tvdd pins must be connected to tvdd, which must be 3.3v. tvss1 47 n6, p6 tvss2 50 l6, m6 tvss3 59 l9, m9 tvss4 62 n9, p9 tvss5 119 a9, b9 tvss6 122 c9, d9 tvss7 131 c6, d6 tvss8 134 a6, b6 ? analog ground for transmitters avdd 90 h14 ? 3.3v analog core power supply avss 89 h11 ? analog core ground
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 19 of 97 figure 4-1. 160-pin pbga pin assignment 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a rclk5 rpos5/ rdata5 rneg5/ cv5 tvdd5 tring5 tvss5 rtip5 rtip8 tvss8 tring8 tvdd8 rneg8/ cv8 rpos8/ rdata8 rclk8 b tclk5 tpos5/ tdata5 tneg5 tvdd5 ttip5 tvss5 rring5 rring8 tvss8 ttip8 tvdd8 tneg8 tpos8/ tdata8 tclk8 c rclk6 rpos6/ rdata6 rneg6/ cv6 tvdd6 tring6 tvss6 rtip6 rtip7 tvss7 tring7 tvdd7 rneg7/ cv7 rpos7/ rdata7 rclk7 d tclk6 tpos6/ tdata6 tneg6 tvdd6 ttip6 tvss6 rring6 rring7 tvss7 ttip7 tvdd7 tneg7 tpos7/ tdata7 tclk7 e oe clke rlos6/ scan_di rlos5/ scan_do rlos8/ scan_en rlos7/ scan_clk modesel mclk f jtclk jtdo jtdi jtms a4 gmc3 gmc2 gmc1 g vddio clka jtrstb gndio1 gndio0 gmc0 lp1 vddio0 h avdd scan_ mode motel/ code avss dvss lp2 lp3 dvdd j ts0 ts1 ts2 csb/ jas lp4 lp5 lp6 lp7 k sdo intb rlos3/ rxprobe b1 rlos4/ rxprobe c1 ds26303 hardware mode (bottom view) rlos1/ teclk rlos2/ rxprobe a1 mux/ timprm lp8 l tclk3 tpos3/ tdata3 tneg3 tvdd3 ttip3 tvss3 rring3 rring2 tvss2 ttip2 tvdd2 tneg2 tpos2/ tdata2 tclk2 m rclk3 rpos3/ rdata3 rneg3/ cv3 tvdd3 tring3 tvss3 rtip3 rtip2 tvss2 tring2 tvdd2 rneg2/ cv2 rpos2/ rdata2 rclk2 n tclk4 tpos4/ tdata4 tneg4 tvdd4 ttip4 tvss4 rring4 rring1 tvss1 ttip1 tvdd1 tneg1 tpos1/ tdata1 tclk1 p rclk4 rpos4/ rdata4 rneg4/ cv4 tvdd4 tring4 tvss4 rtip4 rtip1 tvss1 tring1 tvdd1 rneg1/ cv1 rpos1/ rdata1 rclk1
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 20 of 97 figure 4-2. 144-pin elqfp pin assignment name pin name pin name pin name pin tpos8/tdata8 1 tpos1/tdata1 37 tpos4/tdata4 73 tneg5 109 tclk8 2 tneg1 38 tclk4 74 rclk5 110 rlos7 3 rclk1 39 rlos3/rxprobeb1 75 rpos5/rdata5 111 rneg7/cv7 4 rpos1/rdata1 40 rneg3/cv3 76 rneg5/cv5 112 rpos7/rdata7 5 rneg1/cv1 41 rpos3/rdata3 77 rlos5 113 rclk7 6 rlos1/teclk 42 rclk3 78 oe 114 tneg7 7 mux/timprm 43 tneg3 79 clke 115 tpos7/tdata7 8 tvdd1 44 tpos3/tdata3 80 tvdd5 116 tclk7 9 ttip1 45 tclk3 81 ttip5 117 mclk 10 tring1 46 intb 82 tring5 118 modesel 11 tvss1 47 sd0/rdy/ackb/ rimoff 83 tvss5 119 a4/rimpmsb 12 rtip1 48 sdi/wrb/dsb/ts0 84 rtip5 120 a3/gmc3 13 rring1 49 rdb/rwb/ts1 85 rring5 121 a2/gmc2 14 tvss2 50 sclk/ale/asb/ts2 86 tvss6 122 a1/gmc1 15 tring2 51 csb/jas 87 tring6 123 a0/gmc0 16 ttip2 52 motel/code 88 ttip6 124 vddio 17 tvdd2 53 avss 89 tvdd6 125 vssio 18 rring2 54 avdd 90 rring6 126 dvdd 19 rtip2 55 vssio 91 rtip6 127 dvss 20 tvdd3 56 vddio 92 tvdd7 128 d0/ad0/lp1 21 ttip3 57 clka 93 ttip7 129 d1/ad1/lp2 22 tring3 58 scan_mode 94 tring7 130 d2/ad2/lp3 23 tvss3 59 jtrstb 95 tvss7 131 d3/ad3/lp4 24 rtip3 60 jtms 96 rtip7 132 d4/ad4/lp5 25 rring3 61 jtclk 97 rring7 133 d5/ad5/lp6 26 tvss4 62 jtdo 98 tvss8 134 d6/ad6/lp7 27 tring4 63 jtdi 99 tring8 135 d7/ad7/bswp/lp8 28 ttip4 64 tclk6 100 ttip8 136 tclk2 29 tvdd4 65 tpos6/tdata6 101 tvdd8 137 tpos2/tdata2 30 rring4 66 tneg6 102 rring8 138 tneg2 31 rtip4 67 rclk6 103 rtip8 139 rclk2 32 rlos4/rxprobec1 68 rpos6/rdata6 104 rlos8 140 rpos2/rdata2 33 rneg4/cv4 69 rneg6/cv6 105 rneg8/cv8 141 rneg2/cv2 34 rpos4/rdata4 70 rlos6 106 rpos8/rdata8 142 rlos2/rxprobea1 35 rclk4 71 tclk5 107 rclk8 143 tclk1 36 tneg4 72 tpos5/tdata5 108 tneg8 144
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 21 of 97 4.1 hardware and host port operation 4.1.1 hardware mode the ds26303 supports a hardware configuration mode that allows the user to configure the device through setting levels on the device?s pins. this mode allows the configuration of the ds26303 without the use of a microprocessor. not all of the device features are supported in the hardware mode. to see all available options for this hardware mode, see the pin descriptions in table 4-1 . the following table provides two basic examples of configurations available in hardware mode by setting pins. table 4-2. hardware mode configuration examples standard mode configuration pin name, hardware mode t1 e1 notes ttip[8:1] output output ? tring[8:1] output output ? rtip[8:1] input input ? rring[8:1] input input ? tpos[8:1] input input ? tneg[8:1] input input ? tclk[8:1] input: 1.544mhz input: 2.048mhz ? rpos[8:1] output output ? rneg[8:1] output output ? rclk[8:1] output: 1.544mhz output: 2.048mhz ? mclk input: 1.544mhz input: 2.048mhz used as recovery clock. rlos [8:1] output output meets t1.231 and itu g.775. modesel 0 0 low for hardware mode. timprm 0 0 (part number ends in ?75) 100 for t1 mode/75 e1 mode. code 1 1 ami endocoding/decoding. jas n.c.: pulled to vddio/2 n.c.: pulled to vddio/2 jitter attenuator is not used. ts[2:0] 111 000 set template t1 (655ft)-100 /e1-75 rimpoff 0 0 receive impedance should default to on. intb n.c. n.c. not used in hardware mode. lp[8:1] n.c.: pulled to vddio/2 n.c.: pulled to vddio/2 internally pulled to vddio/2. rimpms 0 0 internal impedance mode selected. gmc[3:0] 0000 0000 no monitoring enabled. oe 1 1 ttip and tring are outputs. clke 0 0 rposn/rnegn are clocked on rising edge. jtrstb input, pulled up input, pulled up jtag. jtms input input jtclk input input jtdo output, high-z output, high-z jtdi input, pulled up input, pulled up rstb input, pullup input, pullup reset. clka n.c. n.c. not available in hardware node. scan_mode 0 0 pull low or ground. used only in factory test.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 22 of 97 4.1.2 serial port operation setting modesel = vddio/2 enables the serial bus interface on the ds26303. port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. see section 10.3 for the ac timing of the serial port. all serial port accesses are lsb first when bswp pin is low and msb first when bswp is high. figure 4-3 to figure 4-5 show operation with lsb first. this port is compatible with the spi interface defined for motorola processors. an example of this is motorola?s mmc2107. reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. the first bit written (lsb) of the address/command byte specifies whether the access is a read (1) or a write (0). the next 5 bits identify the register address (a1 to a5; a6 and a7 are ignored). all data transfers are initiated by driving the csb input low. when clke is low, sdo data is output on the rising edge of sclk and when clke is high, data is output on the falling edge of sclk. data is held until the next falling or rising edge. all data transfers are terminated if csb input transitions high. port control logic is disabled and sdo is tri-stated when csb is high. sdi is always sampled on the rising edge of sclk. figure 4-3. serial port operation for write access 12345678910 111213141516 sclk csb 0 a1 a2 a3 a4 a5 a6 x (msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled figure 4-4. serial port operation for read access with clke = 0 12345678910111213141516 0 a1 a2 a3 a4 a5 d1 d2 d3 d4 d5 d6 sclk sdi sdo csb (lsb) (msb) d0 (lsb) d7 (msb) a6 x read access enabled
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 23 of 97 figure 4-5. serial port operation for read access with clke = 1 12345678910111213141516 0 a1 a2 a3 a4 a5 d1 d2 d3 d4 d5 d6 sclk sdi sdo csb (lsb) (msb) d0 (lsb) d7 (msb) a6 x 4.1.3 parallel port operation when using the parallel interface on the ds26303 the user has the option for either multiplexed bus operation or nonmultiplexed bus operation. the ale pin is pulled high in nonmultiplexed bus operation. the ds26303 can operate with either intel or motorola bus-timing configurations selected by motel pin. this pin being high selects the intel mode. the parallel port is only operational if modesel pin is pulled high. the following table lists all the pins and their functions in the parallel port mode. see the timing diagrams in section 10 for more details. table 4-3. parallel port m ode selection and pin functions modesel, motel, mux parallel host interface address, data, and control 100 nonmultiplexed motorola csb, ackb, dsb, rwb, asb, a [4:0], d [7:0], intb 110 nonmultiplexed intel csb, rdy, wrb, rdb, ale, a [4:0], d [7:0], intb 101 multiplexed motorola csb, ackb, dsb, rwb, asb, ad [7:0], intb 111 multiplexed intel csb, rdy, wrb, rdb, ale, ad [7:0], intb 4.1.4 interrupt handling there are four sets of events that can potentially trigger an interrupt. the interrupt functions as follows: when status changes on an interruptible event, the intb pin will go low if the event is enabled through the corresponding interrupt-enable register. intb must be pulled high externally with a 10k resistor for wired-or operation. if a wired-or operation is not required, the intb pin can be configured to be high when not active by setting register gisc.intm . when an interrupt occurs, the host processor must read the interrupt status register to determine the source of the interrupt. the read also clears the interrupt status register and clears the output intb pin. the interrupt status register can also be configured as clear-on-write as per register gisc.cwe . this clears intb when a clear-on-write is performed. subsequently, the host processor can read the corresponding status register to check the real-time status of the event.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 24 of 97 figure 4-6. interrupt handling flow diagram interrupt allowed interrupt conditon exist? read interrupt status register read corresponding status register (optional) service the interrupt no yes
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 25 of 97 5 registers five address bits are used to control the settings of the registers. in the parallel nonmultiplexed mode, ad[4:0] is used. in multiplexed mode, ad[4:0] is used and ad[5:1] is used in serial mode.the register space contains control for channels 1 to 8 from address 00 hex to 1f hex. the addp (1f) register is used as a pointer to access the different banks of registers. this register must be set to aa hex for access of the secondary bank of registers, 01 hex for access to the individual liu bank of registers, and 02 hex for access of the bert bank of registers. the primary bank of registers is accessed upon reset of this register to 00 hex. table 5-1. primary register set address name symbol hex parallel interface a7?a0 (hex) serial interface a7?a1 (hex) rw identification id 00 xxx00000 xx00000 r analog loopback configuration albc 01 xxx00001 xx00001 rw remote loopback configurat ion rlbc 02 xxx00010 xx00010 rw transmit all-ones enable taoe 03 xxx00011 xx00011 rw los status loss 04 xxx00100 xx00100 r driver fault monitor status dfms 05 xxx00101 xx00101 r los interrupt enable losie 06 xxx00110 xx00110 rw driver fault monitor interrupt enable dfmie 07 xxx00111 xx00111 rw los interrupt status losis 08 xxx01000 xx01000 r driver fault monitor interrupt status dfmis 09 xxx01001 xx01001 r software reset swr 0a xxx01010 xx01010 w g.772 monitor configuration gmc 0b xxx01011 xx01011 rw digital loopback configuration dlbc 0c xxx01100 xx01100 rw los/ais criteria selection lascs 0d xxx01101 xx01101 rw automatic transmit all-ones select ataos 0e xxx01110 xx01110 rw global configuration gc 0f xxx01111 xx01111 rw template select transceiver register tst 10 xxx10000 xx10000 rw template select ts 11 xxx10001 xx10001 rw output-enable bar oeb 12 xxx10010 xx10010 rw alarm indication signal ais 13 xxx10011 xx10011 r ais interrupt enable aisie 14 xxx10100 xx10100 rw ais interrupt status aisis 15 xxx10101 xx10101 r reserved ? 16?1e xxx10110? xxx11110 xx10110? xx11110 ? address pointer for secondary register set addp 1f xxx11111 xx11111 rw
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 26 of 97 table 5-2. secondary register set address name symbol hex parallel interface a7?a0 (hex) serial interface a7?a1 (hex) rw single rail-mode select srms 00 xxx00000 xx00000 rw line code selection lcs 01 xxx00001 xx00001 rw not used ? 02 xxx00010 xx00010 ? receive power-down enable rpde 03 xxx00011 xx00011 rw transmit power-down enable tpde 04 xxx00100 xx00100 rw excessive zero detect enable ezde 05 xxx00101 xx00101 rw code violation detect enable bar cvdeb 06 xxx00110 xx00110 rw not used ? 07?1e xxx00111? xxx11110 xx00111? xx11110 ? address pointer for secondary register set addp 1f xxx11111 xx11111 rw table 5-3. individual liu register set address name symbol hex parallel interface a7?a0 (hex) serial interface a7?a1 (hex) rw individual ja enable ijae 00 xxx00000 xx00000 rw individual ja position select ijaps 01 xxx00001 xx00001 rw individual ja fifo depth select ijafds 02 xxx00010 xx00010 rw individual ja fifo limit trip ijaflt 03 xxx00011 xx00011 r individual short circuit protection disable iscpd 04 xxx00100 xx00100 rw individual ais select iaisel 05 xxx00101 xx00101 rw master clock select mc 06 xxx00110 xx00110 rw global management register gmr 07 xxx00111 xx00111 rw reserved reserved 08?0b xxx01000? xxx01011 xx01000? xx01011 rw reserved reserved 0c?0f xxx01100? xxx01111 xx01100? xx01111 r bit error rate tester control register btcr 10 xxx10000 xx10000 rw line violation detect status lvds 12 xxx10010 xx10010 r receive clock invert rclki 13 xxx10011 xx10011 rw transmit clock invert tclki 14 xxx10100 xx10100 rw clock control regist er ccr 15 xxx10101 xx10101 rw rclk disable upon los register rdulr 16 xxx10110 xx10110 rw global interrupt status control gisc 1e xxx11110 xx11110 rw address pointer for secondary register set addp 1f xxx11111 xx11111 rw
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 27 of 97 table 5-4. bert register set address name symbol hex parallel interface a7?a0 (hex) serial interface a7?a1 (hex) rw bert control register bcr 00 xxx00000 xx00000 rw reserved ? 01 xxx00001 xx00001 bert pattern configuration 1 bpcr1 02 xxx00010 xx00010 rw bert pattern configuration 2 bpcr2 03 xxx00011 xx00011 rw bert seed/pattern 1 bspr1 04 xxx00100 xx00100 rw bert seed/pattern 2 bspr2 05 xxx00101 xx00101 rw bert seed/pattern 3 bspr3 06 xxx00110 xx00110 rw bert seed/pattern 4 bspr4 07 xxx00111 xx00111 rw transmit error insertion control teicr 08 xxx01000 xx01000 rw reserved ? 09?0a xxx01001? xx01010 ? ? bert status register bsr 0c xxx01100 xx01100 r reserved 0d xxx01101 xx01101 bert status register lat ched bsrl 0e xxx10011 xx10011 rw bert status register interrupt enable bsrie 10 xxx10000 xx10000 rw reserved ? 11?13 xxx10001? xxx10011 xx10001? xx10011 ? receive bit error count register 1 rbecr1 14 xxx10100 xx10100 r receive bit error count register 2 rbecr2 15 xxx10101 xx10101 r receive bit error count register 3 rbecr3 16 xxx10110 xx10110 r receive bit error count register 4 rbecr4 17 xxx10111 xx10111 r receive bit count register 1 rbcr1 18 xxx11000 xx11000 r receive bit count register 2 rbcr2 19 xxx11001 xx11001 r receive bit count register 3 rbcr3 1a xxx11010 xx11010 r receive bit count register 4 rbcr4 1b xxx11011 xx11011 r reserved ? 1c?1e xxx11100? xxx11110 xx11100? xx11110 ? address pointer for secondary register set addp 1f xxx11111 xx11111 rw
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 28 of 97 table 5-5. primary register set bit map register address type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id 00 r id7 id6 id5 id4 id3 id2 id1 id0 albc 01 rw alc8 albc7 albc6 albc5 albc4 albc3 albc2 albc1 rlbc 02 rw rlbc8 rlbc7 rlbc6 rlbc5 rlbc4 rlbc3 rlbc2 rlbc1 taoe 03 rw taoe8 taoe7 taoe6 taoe5 taoe4 taoe3 taoe2 taoe1 loss 04 rw loss8 loss7 loss6 loss5 loss4 loss3 loss2 loss1 dfms 05 rw dfms8 dfms7 dfms6 dfms5 dfms4 dfms3 dfms2 dfms1 losie 06 rw losie8 losie7 losie6 losie5 losie4 losie3 losie2 losie1 dfmie 07 rw dfmie8 dfmie7 dfmie6 dfmie5 dfmie4 dfmie3 dfmie2 dfmie1 losis 08 r losis8 losis7 losis6 losis5 losis4 losis3 losis2 losis1 dfmis 09 r dfmis8 dfmis7 dfmis6 dfmis5 dfmis4 dfmis3 dfmis2 dfmis1 swr 0a w swr8 swr7 swr6 swr5 swr4 swr3 swr2 swr1 gmc 0b rw ? ? ? ? gmc4 gmc3 gmc2 gmc1 dlbc 0c rw dlbc8 dlbc7 dlbc6 dlbc5 dlbc4 dlbc3 dlbc2 dlbc1 lascs 0d rw lascs8 lascs7 lascs6 lascs5 lascs4 lascs3 lascs2 lascs1 ataos 0e rw ataos8 ataos7 ataos6 at aos5 ataos4 ataos3 ataos2 ataos1 gc 0f rw rimpms aisel scpd code jads ? japs jae tst 10 rw ? ? ? ? ? tst2 tst1 tst0 ts 11 rw rimpoff timpoff t1mode timprm1 timprm ts2 ts1 ts0 oeb 12 rw oeb8 oeb7 oeb6 oeb5 oeb4 oeb3 oeb2 oeb1 ais 13 r ais8 ais7 ais6 ais5 ais4 ais3 ais2 ais1 aisie 14 rw aisie8 aisie7 aisie6 aisie5 aisie4 aisie3 aisie2 aisie1 aisi 15 r aisi8 aisi7 aisi6 aisi5 aisi4 aisi3 aisi2 aisi1 not used 16-1e ? ? ? ? ? ? ? ? ? addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 table 5-6. secondary register set bit map register address type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srs 00 rw srms8 srms7 srms6 srms5 srms4 srms3 srms2 srms1 lcs 01 rw lcs8 lcs7 lcs6 lcs5 lsc4 lcs3 lsc2 lsc1 not used 02 rw ? ? ? ? ? ? ? ? rpde 03 rw rpde8 rpde7 rpde6 rpde5 rpde4 rpde3 rpde2 rpde1 tpde 04 rw tpde8 tdpe7 tpde6 tpde5 tpde4 tpde3 tpde2 tpde1 ezde 05 rw ezde8 ezde7 ezde6 ezde5 ezde4 ezde3 ezde2 ezde1 cvdeb 06 rw cvdeb8 cvdeb7 cvdeb6 cvdeb5 cvdeb4 cvdeb3 cvdeb2 cvdeb1 not used 07-1e ? ? ? ? ? ? ? ? ? addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 table 5-7. individual li u register set bit map register address type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ijae 00 rw ijae8 ijae7 ijae6 ijae5 ijae4 ijae3 ijae2 ijae1 ijaps 01 rw ijaps8 ijaps7 ijaps6 ijaps5 ijaps4 ijaps3 ijaps2 ijaps1 ijafds 02 rw ijafds8 ijafds7 ijafds6 ijafds5 ijafds4 ijafds3 ijafds2 ijafds1 ijaflt 03 r ijaflt8 ijaflt7 ijaflt6 ijaflt5 ijaflt4 ijaflt3 ijaflt2 ijaflt1 iscpd 04 rw iscpd8 iscpd7 iscpd6 iscpd5 iscpd4 iscpd3 iscpd2 iscpd1 iaisel 05 rw iaisel8 iaisel7 iaisel6 iaisel5 iaisel4 iaisel3 iaisel2 iaisel1 mc 06 rw ? pclki teclke clkae mps1 mps0 freqs plle gmr 07 rw ? ? ? ? ? ? ? rhpmc reserved 08 rw ? ? ? ? ? ? ? ? reserved 09 rw ? ? ? ? ? ? ? ? reserved 0a rw ? ? ? ? ? ? ? ? reserved 0b rw ? ? ? ? ? ? ? ? reserved 0c r ? ? ? ? ? ? ? ? reserved 0d r ? ? ? ? ? ? ? ? reserved 0e r ? ? ? ? ? ? ? ? reserved 0f r ? ? ? ? ? ? ? ? btcr 10 rw bts2 bts1 bts0 ? ? ? ? berte beir 11 rw beir8 beir7 beir6 beir5 beir4 beir3 beir2 beir1 lvds 12 r lvds8 lvds7 lvds6 lvds5 lvds4 lvds3 lvds2 lvds1 rclki 13 rw rclki8 rclki7 rclki6 rclki5 rclki4 rclki3 rclki2 rclki1 tclki 14 rw tclki8 tclki7 tclki6 tc lki5 tclki4 tclki3 tclki2 tclki1 ccr 15 rw pclks2 pclks1 pclks0 teclks clka3 clka2 clka1 clka0 rdulr 16 rw rdulr8 rdulr7 rdulr6 rdulr5 rdulr4 rdulr3 rdulr2 rdulr1 gisc 1e rw ? ? ? ? ? ? intm cwe addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 29 of 97 table 5-8. bert register bit map register address type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bcr 00 rw pmum lpmu rnpl rpic mpr aprd tnpl tpic not used 01 ? ? ? ? ? ? ? ? ? bpcr1 02 rw ? qrss pts plf4 plf3 plf2 plf1 plf0 bpcr2 03 ? ? ? ? ptf4 ptf3 ptf2 ptf1 ptf0 bspr1 04 rw bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 bspr2 05 ? bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 bspr3 06 rw bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 bspr4 07 ? bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 teicr 08 rw ? ? teir2 teir1 teir0 bei tsei meims not used 09?0b ? ? ? ? ? ? ? ? ? bsr 0c r/w ? ? ? ? pms ? bec oos not used 0d ? ? ? ? ? ? ? ? ? bsrl 0e rl/w ? ? ? ? pmsl bel becl oosl not used 0f ? ? ? ? ? ? ? ? ? bsrie 10 rw ? ? ? ? pmsie beie becie oosie not used 11?13 ? ? ? ? ? ? ? ? ? rbecr1 14 r bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 rbecr2 15 r bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 rbecr3 16 r bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 not used 17 ? ? ? ? ? ? ? ? ? rbcr1 18 r bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 rbcr2 19 r bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 rbcr3 1a r bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 rbcr4 1b r bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 not used 1c?1e ? ? ? ? ? ? ? ? ? addp 1f rw addp7 addp6 addp5 addp4 addp3 addp2 addp1 addp0 note: underlined bits are read-only.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 30 of 97 5.1 register description this section details the register description of each bit. whenever the variable ? n? in italics is used in any of the register descriptions, it represents 1, 2, 3, 4, 5, 6, 7, and 8. 5.1.1 primary registers register name: id register description: id register register address: 00h bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 bit 7: device code id bit 7 (id7). this bit is zero for the 75 impedance part number and one for the 120 impedance part number. bits 6 to 3: device code id bits 6 to 3 (id6 to id3). these bits tell the user the number of ports the device contains. bits 2 to 0: device code id bits 2 to 0 (id2 to id0). these bits tell the user the revision of the part. contact the factory for details. register name: albc register description: analog loopback control register address: 01h bit # 7 6 5 4 3 2 1 0 name albc8 albc7 albc6 albc 5 albc4 albc3 albc2 albc1 default 0 0 0 0 0 0 0 0 bits 7 to 0: analog loopback control bits channel n (albc n ). when this bit is set, liu n is placed in analog loopback. ttip and tring are looped back to rtip and rring. the data at rtip and rring is ignored. los detector is still in operation. the jitter attenuator is in use if enabled for the transmitter or receiver. register name: rlbc register description: remote loopback control register address: 02h bit # 7 6 5 4 3 2 1 0 name rlbc8 rlbc7 rlbc6 rlbc5 rlbc4 rlbc3 rlbc2 rlbc1 default 0 0 0 0 0 0 0 0 bits 7 to 0: remote loopb ack control bits channel n (rlbc n ). when this bit is set, remote loopback is enabled on liu n . the analog-received signal goes through the receive digital and is looped back to the transmitter. the data at tpos and tneg is ignored. the jitter attenuator is in use if enabled.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 31 of 97 register name: taoe register description: transmit all-ones enable register address: 03h bit # 7 6 5 4 3 2 1 0 name taoe8 taoe7 taoe6 taoe5 taoe4 taoe3 taoe2 taoe1 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit all-ones enable channel n (taoe n ). when this bit is set, a continuous stream of all ones on ttip and tring are sent on channel n . mclk is used as a reference clock for the transmit all-ones signal. the data arriving at tpos and tneg is ignored. register name: loss register description: loss-of-signal status register address: 04h bit # 7 6 5 4 3 2 1 0 name los8 los7 los6 los5 los4 los3 los2 los1 default 0 0 0 0 0 0 0 0 bits 7 to 0: loss-of-signal status channel n (los n ). when this bit is set, an los condition has been detected on liu n . the criteria and conditions of los are described in section 6.4.3 : loss of signal . register name: dfms register description: driver fault monitor status register address: 05h bit # 7 6 5 4 3 2 1 0 name dfms8 dfms7 dfms6 dfms5 dfms4 dfms3 dfms2 dfms1 default 0 0 0 0 0 0 0 0 bits 7 to 0: driver fault monitor status channel n (dfms n ). when this bit is set, it indicates that there is a short circuit at the transmit driver for liu n . register name: losie register description: loss-of-signal interrupt enable register address: 06h bit # 7 6 5 4 3 2 1 0 name losie8 losie7 losie6 losie5 losie4 losie3 losie2 losie1 default 0 0 0 0 0 0 0 0 bits 7 to 0: loss-of-signal interrupt enable channel n (losie n ). when this bit is set, a change in the los status for liu n can generate an interrupt.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 32 of 97 register name: dfmie register description: driver fault monitor interrupt enable register address: 07h bit # 7 6 5 4 3 2 1 0 name dfmie8 dfmie7 dfmie6 dfmie5 dfmie4 dfmie3 dfmie2 dfmie1 default 0 0 0 0 0 0 0 0 bits 7 to 0: driver fault monitor interrupt enable channel n (dfmie n ) . when this bit is set, a change in dfm status can generate an interrupt in monitor n . register name: losis register description: loss-of-signal interrupt status register address: 08h bit # 7 6 5 4 3 2 1 0 name losis8 losis7 losis6 losis5 losis4 losis3 losis2 losis1 default 0 0 0 0 0 0 0 0 bits 7 to 0: loss-of-signal interrupt status channel n (losis n ) . when this bit is set, it indicates an los status has transitioned from a 0 to 1 or 1 to 0 and was detected for liu n . the bit for liu n is enabled by register losie(06h). this bit when latched is cleared on a read operation. register name: dfmis register description: driver fault monitor interrupt status register address: 09h bit # 7 6 5 4 3 2 1 0 name dfmis8 dfmis7 dfmis6 dfmis5 dfmis4 dfmis3 dfmis2 dfmis1 default 0 0 0 0 0 0 0 0 bits 7 to 0: driver fault status register channel n (dfmis n ) . when this bit is set, it indicates a dfm status has transitioned from ?0 to 1? or ?1 to 0? and was detected for liu n . the bit for liu n is enabled by register dfmie(07h). this bit when latched is cleared on a read operation. register name: swr register description: software reset register address: 0ah bit # 7 6 5 4 3 2 1 0 name swr8 swr7 swr6 swr5 swr4 swr3 swr2 swr1 default 0 0 0 0 0 0 0 0 bits 7 to 0: software reset (swr) . whenever any write is performed to this register, at least a 1 s reset will be generated that resets the ds26303. all the registers will be restored to their default values. a read operation will always read back all zeros.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 33 of 97 register name: gmc register description: g.772 monitoring control register address: 0bh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? gmc3 gmc2 gmc1 gmc0 default 0 0 0 0 0 0 0 0 bits 3 to 0: g.772 monitoring control (gmc) . these bits are used to select transmitter or receiver for nonintrusive monitoring. receiver 1 is used to monitor channels 2 to 8 of one receiver from rtip2? rtip8/rring2?rring8 or of one transmitter from ttip2?ttip8/tring2?tring8. see table 5-9 . table 5-9. g.772 monitoring control gmc3 gmc2 gmc1 gmc0 selection 0 0 0 0 no monitoring 0 0 0 1 receiver 2 0 0 1 0 receiver 3 0 0 1 1 receiver 4 0 1 0 0 receiver 5 0 1 0 1 receiver 6 0 1 1 0 receiver 7 0 1 1 1 receiver 8 1 0 0 0 no monitoring 1 0 0 1 transmitter 2 1 0 1 0 transmitter 3 1 0 1 1 transmitter 4 1 1 0 0 transmitter 5 1 1 0 1 transmitter 6 1 1 1 0 transmitter 7 1 1 1 1 transmitter 8 register name: dlbc register description: digital loopback control register address: 0ch bit # 7 6 5 4 3 2 1 0 name dlbc8 dlbc7 dlbc6 dlbc5 dlbc4 dlbc3 dlbc2 dlbc1 default 0 0 0 0 0 0 0 0 bits 7 to 0: digital loopback control channel n (dlbc n ) . when this bit is set, the liu n is placed in digital loopback. the data at tpos/tneg is encoded and looped back to the decoder and output on rpos/rneg. the jitter attenuator can optionally be included in the transmit or receive paths. register name: lascs register description: los/ais criteria selection register address: 0dh bit # 7 6 5 4 3 2 1 0 name lascs8 lascs7 lascs6 lascs5 lascs4 lascs3 lascs2 lascs1 default 0 0 0 0 0 0 0 0 bits 7 to 0: los/ais criteria selection channel n (lascs n ) . this bit is used for los/ais selection criteria for liu n . in e1 mode if set, these bits use etsi (300233) mode selections. if reset, these bits use g.775 criteria. in t1/j1 mode, t1.231 criteria is selected.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 34 of 97 register name: ataos register description: automatic transmit all-ones select register address: 0eh bit # 7 6 5 4 3 2 1 0 name ataos8 ataos7 ataos6 ataos5 ataos4 ataos3 ataos2 ataos1 default 0 0 0 0 0 0 0 0 bit 7 to 0: automatic transmit all-ones select channel n (ataos n ) . when this bit is set an all-ones signal is sent if a loss of signal is detected for liu n . all-ones signal uses mclk as the reference clock. register name: gc register description: global configuration register address: 0fh bit # 7 6 5 4 3 2 1 0 name rimpms aisel scpd code jads ? japs jae default 0 0 0 0 0 0 0 0 bit 7: receive impedance mode select (rimpms) . when this bit is set, the internal impedance mode is selected, so rtip and ring require no external resistance component. when this mode is selected, the die attach pad on the bottom of the package should be connected to ground for thermal dissipation. when reset, external impedance mode is selected so rtip and ring require external resistance. note that when in external impedance mode, the resistance is still adjusted internally for the t1 (100 ), j1 (110 ), and e1(75 ) modes of operation by the template selected so that only one resistor value is required externally. in e1 (120 ), external impedance mode has no need for any internal adjustment. bit 6: ais enable during loss (aisel) . when this bit is set, an ais is sent to the system side upon detecting an los for each channel. the individual liu register iaisel settings are ignored when this bit is set. when reset, the iaisel register has control. bit 5: short-circuit-protection disable (scpd). if this bit is set, the short-circuit protection is disabled for all the transmitters. the individual liu register iscpd settings are ignored when this bit is set. when reset, the iscpd register has control. bit 4: code (code). if this bit is set, ami encoder/decoder is selected. the lcs register settings are ignored when this bit is set. if reset, the lcs register has control. bit 3: jitter attenuator depth select (jads) . if this bit is set the jitter attenuator fifo depth is 128 bits. the settings in the ijafds register are ignored if this register is set. if reset, the ijafds register has control. bit 1: jitter attenuator position select (japs). when the japs bit is set high, the ja is in the receive path, and when it is default or set low, it is in the transmit path. these settings can be changed for an individual liu by settings in register ijaps . note that when bit jae is set, the settings in register ijaps are ignored. bit 0: jitter attenuator enable (jae). when this bit is set the ja is enabled. the settings in the ijae register are ignored if this register is set. if reset, the ijae register has control.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 35 of 97 register name: tst register description: template select transmitter register register address: 10h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? tst2 tst1 tst0 default 0 0 0 0 0 0 0 0 bits 2 to 0: tst template select transceiver [2:0] (tst [2:0]) . tst[2:0] is used to select the transceiver that the transmit template select register (hex 11) applies to. see table 5-10 . table 5-10. tst template select transmitter register tst[2:0] channel tst[2:0] channel 000 1 100 5 001 2 101 6 010 3 110 7 011 4 111 8 register name: ts register description: template select register register address: 11h bit # 7 6 5 4 3 2 1 0 name rimpoff timpoff ? ? timprm ts2 ts1 ts0 default 0 0 ? ? 0 0 0 0 bit 7: receive impedance match off (rimpoff). if this bit is set, all the receive impedance match is turned off. bit 6: transmit impedance termination off (timpoff). if this bit is set, all the internal transmit terminating impedance is turned off. bits 5 and 4: reserved bit 3: transmit impedance receive match (timprm). this bit selects the internal transmit termination impedance and receive impedance match for e1 mode and t1/j1 mode. note: if the part number ends with ?120, then the default is 120 and 75 when set for el mode only. device bit setting e1 mode ( ) t1 mode ( ) ds26303l-120 0 120 100 ds26303l-120 1 75 110 ds26303l-75 0 75 100 ds26303l-75 1 120 110 bits 2 to 0: template selection [2:0] (ts[2:0]). bits ts[2:0] are used to select e1 or t1/j1 mode, the template, and the settings for various cable lengths. the impedance termination for the transmitter and impedance match for the receiver are specified by bit timprm. see table 5-11 for bit selection of ts[2:0].
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 36 of 97 table 5-11. template selection ts[2:0] line length cable loss (db) impedance ( ) 1 operation mode 011 0?133ft. abam 0.6 100/110 t1/j1 100 133?266ft. abam 1.2 100/110 t1 101 266?399ft. abam 1.8 100/110 t1 110 399?533ft. abam 2.4 100/110 t1 111 533?655ft. abam 3.0 100/110 t1 000 g.703 coaxial and twisted pair cable 75/120 e1 001 and 010 reserved ? ? ? 1 see timprm bit in swm or timprm pin in hwm for transmit impedance and receive match selection. register name: oeb register description: output-enable bar register address: 12h bit # 7 6 5 4 3 2 1 0 name oeb8 oeb7 oeb6 oeb5 oeb4 oeb3 oeb2 oeb1 default 0 0 0 0 0 0 0 0 bits 7 to 0: output-enable bar channel n (oeb n ). when this bit is set the transmitter output for liu n is placed in high impedance. note that the oe pin overrides this setting when low. register name: ais register description: alarm indication signal status register address: 13h bit # 7 6 5 4 3 2 1 0 name ais8 ais7 ais6 ais5 ais4 ais3 ais2 ais1 default 0 0 0 0 0 0 0 0 bits 7 to 0: alarm indication signal channel n (ais n ). this bit is set when ais is detected for liu n . the criteria for ais selection is detailed in section 6.4.4 : ais . the selection of the ais criteria is done by settings in lascs (0d) register.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 37 of 97 register name: aisie register description: ais interrupt enable register address: 14h bit # 7 6 5 4 3 2 1 0 name aisie8 aisie7 aisie6 aisie5 aisie4 aisie3 aisie2 aisie1 default 0 0 0 0 0 0 0 0 bits 7 to 0: ais interrupt mask channel n (aisie n ). when this bit is set, interrupts can be generated for liu n if ais status transitions. register name: aisi register description: ais interrupt register address: 15h bit # 7 6 5 4 3 2 1 0 name aisi8 aisi7 aisi6 aisi5 aisi4 aisi3 aisi2 aisi1 default 0 0 0 0 0 0 0 0 bits 7 to 0: ais interrupt channel n (aisi n ). this bit is set when ais transitions from a 0 to 1 or 1 to 0 and interrupts are enabled by the aisie (14) register for liu n . this bit if set is cleared on a read operation or when the interrupt-enable register is disabled. register name: addp register description: address pointer register address: 1fh bit # 7 6 5 4 3 2 1 0 name addp7 addp6 addp5 addp 4 addp3 addp2 addp1 addp0 default 0 0 0 0 0 0 0 0 bits 7 to 0: address pointer (addp). this pointer is used to switch between pointing to the primary registers, the secondary registers, individual registers, bert registers, and all the test registers. see table 5-12 for bank selection. table 5-12. address pointer bank selection addp7 to addp0 (hex) bank name 00 primary bank aa secondary bank 01 individual liu bank 02 bert bank 03 global test bank 04 liu1 test bank 05 liu2 test bank 06 liu3 test bank 07 liu4 test bank 08 liu5 test bank 09 liu6 test bank 0a liu7 test bank 0b liu8 test bank
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 38 of 97 5.1.2 secondary registers register name: srms register description: single-rail mode select register address: 00h bit # 7 6 5 4 3 2 1 0 name srms8 srms7 srms6 srms5 srms4 srms3 srms2 srms1 default 0 0 0 0 0 0 0 0 bits 7 to 0: single-rail mode select channel n (srms n ). when this bit is set, single-rail mode is selected for the system transmit and receive n . if this bit is reset, dual-rail mode is selected. register name: lcs register description: line code selection register address: 01h bit # 7 6 5 4 3 2 1 0 name lcs8 lcs7 lcs6 lcs5 lcs4 lcs3 lcs2 lcs1 default 0 0 0 0 0 0 0 0 bits 7 to 0: line code select channel n (lcs n ). when this bit is set, ami encoding/decoding is selected for liu n . if reset b8zs or hdb3 encoding/decoding is selected for liu n . note that if the gc .code (0f) register is set it will ignore this register. register name: rpde register description: receive power-down enable register address: 03h bit # 7 6 5 4 3 2 1 0 name rpde8 rpde7 rpde6 rpde 5 rpde4 rpde3 rpde2 rpde1 default 0 0 0 0 0 0 0 0 bits 7 to 0: receive power-down enable channel n (rpde n ). when this bit is set, the receiver for liu n is powered down. register name: tpde register description: transmit power-down enable register address: 04h bit # 7 6 5 4 3 2 1 0 name tpde7 tpde6 tpde5 tpde 4 tpde3 tpde2 tpde1 tpde0 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit power-down enable channel n (tpde n ). when this bit is set, the transmitter for liu n is powered down.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 39 of 97 register name: ezde register description: excessive zero detect enable register address: 05h bit # 7 6 5 4 3 2 1 0 name exzde8 exzde7 exzde6 exzde5 exzde4 exzde3 exzde2 exzde1 default 0 0 0 0 0 0 0 0 bits 7 to 0: excessive zero detect enable channel n (ezde n ). when this bit is reset, excessive zero detection is disabled for liu n . when this bit is set, excessive zero detect enable is enabled. excessive zero detection is only relevant in single-rail mode with hdb3 or b8zs encoding. register name: cvdeb register description: code violation detect enable bar register address: 06h bit # 7 6 5 4 3 2 1 0 name cvdeb8 cvdeb7 cvdeb6 cvdeb5 cvdeb4 cvdeb3 cvdeb2 cvdeb1 default 0 0 0 0 0 0 0 0 bits 7 to 0: code violation detect enable bar channel n (cvdeb n ). if this bit is set, code violation detection is disabled for the liu n . if this bit is reset, code violation detection is enabled. code violation detection is only relevant in single-rail mode with hdb3 encoding. note that if the gc .code register bit is set, it ignored the settings of this register. 5.1.3 individual liu registers register name: ijae register description: individual jitter attenuator enable register address: 00h bit # 7 6 5 4 3 2 1 0 name ijae8 ijae7 ijae6 ijae5 ijae4 ijae3 ijae2 ijae1 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator enable channel n (ijae n ). when this bit is set, the liu jitter attenuator n is enabled. note that if the gc .jae register bit is set, this register is ignored. register name: ijaps register description: individual jitter attenuator position select register address: 01h bit # 7 6 5 4 3 2 1 0 name ijaps8 ijaps7 ijaps6 ijaps5 ijaps4 ijaps3 ijaps2 ijaps1 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator position select channel n (ijaps n ). when this bit is set high, the jitter attenuator is in the receive path n , and when this bit is default or set low the jitter attenuator is in the transmit path n . note that if the gc .jae register bit is set, this register is ignored.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 40 of 97 register name: ijafds register description: individual jitter attenuator fifo depth select register address: 02h bit # 7 6 5 4 3 2 1 0 name ijafds8 ijafds7 ijafds6 ijafds 5 ijafds4 ijafds3 ijafds2 ijafds1 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator fifo depth select n (ijafds n ). when this bit is set for liu n , the jitter attenuator fifo depth is 128 bits. when reset, the jitter attenuator fifo depth is 32 bits. note that if the gc .ijafds register is set, th is register is ignored. register name: ijaflt register description: individual jitter attenuator fifo limit trip register address: 03h bit # 7 6 5 4 3 2 1 0 name ijaflt8 ijaflt7 ijaflt6 ijaflt5 ijaflt4 ijaflt3 ijaflt2 ijaflt1 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual jitter attenuator fifo limit trip n (ijaflt n ). set when the jitter attenuator fifo reaches to within 4 bits of its useful limit for transmitter n . this bit is cleared when read. register name: iscpd register description: individual short-circuit protection disabled register address: 04h bit # 7 6 5 4 3 2 1 0 name iscpd8 iscpd7 iscpd6 iscpd5 iscpd4 iscpd3 iscpd2 iscpd1 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual short-circuit protection disabled n (iscpd n ). when this bit is set, the short-circuit protection is disabled for the individual transmitter n . note that if the gc . scpd register bit is set, the settings in this register are ignored. register name: iaisel register description: individual ais select register address: 05h bit # 7 6 5 4 3 2 1 0 name iaisel8 iaisel7 iaisel6 iaisel5 iaisel4 iaisel3 iaisel2 iaisel1 default 0 0 0 0 0 0 0 0 bits 7 to 0: individual ais enable during loss n (iaisel n ). when this bit is set, individual-ais-enable during loss is enabled for the individual receiver n and ais is sent to the system side upon detection of an los. note that if the gc .aisel register bit is set, the settings in this register are ignored.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 41 of 97 register name: mc register description: master clock select register address: 06h bit # 7 6 5 4 3 2 1 0 name ? pclki teclke clkae mps1 mps0 freqs plle default 0 0 0 0 0 0 0 0 bit 6: pll clock input (pclki). this bit selects the input into to the pll. 0 = mclk is used. 1 = rclk1?rclk8 is used based on the selection in register ccr . bit 5: t1/e1 clock enable (teclke). when this bit is set the teclk output is enabled. if not set teclk is disabled and the teclk output is an rlos output. teclk requires plle to be set for correct functionality. bit 4: clock a enable (clkae). when this bit is set the clka output is enabled. if not set clka is disabled to tri- state. clka requires plle to be set for correct functionality. bits 3 to 2: master period select [1:0] (mps[1:0]). these bits mps[1:0] selects the external mclk frequency for the ds26303. see table 5-13 for details. bit 1: frequency select (freqs). in conjunction with mps[1:0], this bit selects the external mclk frequency for the ds26303. if this bit is set the external master clock can be 1.544mhz or a multiple thereof. if not set the external master clock can be 2.048mhz or a multiple thereof. see table 5-13 for details. bit 0: phase lock loop enable (plle). when this bit is set the phase lock loop is enabled. if not set mclk is the applied input clock. table 5-13. mclk selections plle mps1, mps0 mclk (mhz/50ppm) freqs mode 0 xx 1.544 x t1 0 xx 2.048 x e1 1 00 1.544 1 t1/j1 or e1 1 01 3.088 1 t1/j1 or e1 1 10 6.176 1 t1/j1 or e1 1 11 12.352 1 t1/j1 or e1 1 00 2.048 0 t1/j1 or e1 1 01 4.096 0 t1/j1 or e1 1 10 8.192 0 t1/j1 or e1 1 11 16.384 0 t1/j1 or e1 register name: gmr register description: global management register register address: 07h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? rhpmc default 0 0 0 0 0 0 0 0 bit 0: receive hitless-protection mode control (rhpmc). this bit when set and, when the oe pin goes low, will force all the receivers to turn off any internal impedance matching on rtip and rring. this is used for hitless- protection switching when the user would like a system requiring no external relays in the system.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 42 of 97 register name: btcr register description: bit error-rate tester control register register address: 10h bit # 7 6 5 4 3 2 1 0 name bts2 bts1 bts0 ? ? ? ? berte default 0 0 0 0 0 0 0 0 bits 7 to 5: bit error-rate transceiver select [2:0] (bts[2:0]). these bits bts[2:0] select the liu that the bert applies to. this is only applicable if the berte bit is set. bit 0: bit error-rate tester enable (berte). when this bit is set, the bert is enabled. the bert is only active for one transceiver at a time selected by bts[2:0]. register name: beir register description: bpv error insertion register register address: 11h bit # 7 6 5 4 3 2 1 0 name beir8 beir7 beir6 beir5 beir4 beir3 beir2 beir1 default 0 0 0 0 0 0 0 0 bits 7 to 0: bpv error insertion register n (beir n ). a 0-to-1 transition on this bit causes a single bipolar violation (bpv) to be inserted into the transmit data stream channel n . this bit must be cleared and set again for a subsequent error to be inserted. register name: lvds register description: line violation detect status register address: 12h bit # 7 6 5 4 3 2 1 0 name lvds8 lvds7 lvds6 lvds5 lvds4 lvds3 lvds2 lvds1 default 0 0 0 0 0 0 0 0 bits 7 to 0: line violation detect status n (lvds n ). a bipolar violation, code violation, or excessive zeros cause the associated lvds n bit to latch. this bit is cleared on a read operation. the lvds register captures the first violation within a three-clock-period window. if a second violation occurs after the first violation within the three- clock-period window, then the second violation will not be latched even if a read to the lvds register was performed. excessive zeros need to be enabled by the ezde register for detection by this register. code violations are only relative when in hdb3 mode and can be disabled for detection by this register by setting the cvdeb register. in dual-rail mode only bipolar violations are relevant for this register.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 43 of 97 register name: rclki register description: receive clock invert register address: 13h bit # 7 6 5 4 3 2 1 0 name rclki8 rclki7 rclki6 rclki5 rclki4 rclki3 rclki2 rclki1 default 0 0 0 0 0 0 0 0 bits 7 to 0: receive clock invert n (rclki n ). when this bit is set the rclk for channel n is inverted. this aligns rpos/rneg on the falling edge of rclk. when reset or default, rpos/rneg is aligned on the rising edge of rclk. note that if the clke pin is high, the rpos/rneg is set on the falling edge of rclk regardless of the settings in the register. register name: tclki register description: transmit clock invert register address: 14h bit # 7 6 5 4 3 2 1 0 name tclki8 tclki7 tclki6 tclki5 tclki4 tclki3 tclki2 tclki1 default 0 0 0 0 0 0 0 0 bits 7 to 0: transmit clock invert n (tclki n ). when this bit is set the expected tclk for channel n is inverted. tpos/tneg should be aligned on the rising edge of tclk. when reset or default tpos/tneg should be aligned on the falling edge of tclk.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 44 of 97 register name: ccr register description: clock control register register address: 15h bit # 7 6 5 4 3 2 1 0 name pclks2 pclks1 pclks0 teclks clka3 clka2 clka1 clka0 default 0 0 0 0 0 0 0 0 bits 7 to 5: pll clock select (pclks[2:0]). these bits determine the rclk that is to be used as the input to the pll. if an los is detected for the channel that rclk is recovered from, the pll switches to mclk until the los is cleared. when the los is cleared, rclk is used again. see table 5-14. for rclk selection. table 5-14. pll clock select pclks2 to pclks0 pll clock selected mc. pclki = 1 000 rclk1 001 rclk2 010 rclk3 011 rclk4 100 rclk5 101 rclk6 110 rclk7 111 rclk8 bit 4: t1/e1 clock select (teclks). when this bit is set the t1/e1 clock output is 2.048mhz. when this bit is reset the t1/e1 clock rate is 1.544mhz. bits 3 to 0: clock a select (clka[3:0]). these bits select the output frequency for clka pin. see table 5-15. for available frequencies. table 5-15. clock a select clka3 to clka0 mclk (hz) 0000 2.048m 0001 4.096m 0010 8.192m 0011 16.384m 0100 1.544m 0101 3.088m 0110 6.176m 0111 12.352m 1000 1.536m 1001 3.072m 1010 6.144m 1011 12.288m 1100 32k 1101 64k 1110 128k 1111 256k
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 45 of 97 register name: rdulr register description: rclk disable upon los register register address: 16h bit # 7 6 5 4 3 2 1 0 name rdulr8 rdulr7 rdulr6 rdulr5 rdulr4 rdulr3 rdulr2 rdulr1 default 0 0 0 0 0 0 0 0 bits 7 to 0: rclk disable upon los register n (rdulr n ). when this bit is set the rclk for channel n is disabled upon a loss of signal and set as a low output. when reset or default, rclk switches to mclk upon a loss of signal within 10ms. register name: gisc register description: global interrupt status control register address: 1eh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? intm cwe default 0 0 0 0 0 0 0 0 bit 1: int pin mode (intm). this bit determines the inactive mode of the int pin. the int pin always drives low when active. 0 = pin is high impedance when not active. 1 = pin drives high when not active. bit 0: clear-on-write enable (cwe). when this bit is set, the clear-on-write is enabled for all the latched interrupt status registers. the host processor must write a 1 to the latched interrupt status register bit position before the particular bit is cleared. default for all the latched interrupt status registers is to clear on a read.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 46 of 97 5.1.4 bert registers register name: bcr register description: bert control register register address: 00h bit # 7 6 5 4 3 2 1 0 name pmum lpmu rnpl rpic mpr aprd tnpl tpic default 0 0 0 0 0 0 0 0 bit 7: performance-monitoring update mode (pmum). when 0, a performance-monitoring update is initiated by the lpmu register bit. when 1, a performance-monitoring update is initiated by the receive performance-monitoring update signal (rpmu). note: if rpmu or lpmu is 1, changing the state of this bit may cause a performance- monitoring update to occur. bit 6: local performance-monitoring update (lpmu). this bit causes a performance-monitoring update to be initiated if the local performance-monitoring update is enabled (pmum = 0). a 0-to-1 transition causes the performance-monitoring registers to be updated with the latest data, and the counters reset (0 or 1). for a second performance-monitoring update to be initiated, this bit must be set to 0, and back to 1. if lpmu goes low before the pms bit goes high, an update might not be performed. this bit has no affect when pmum = 1. bit 5: receive new pattern load (rnpl). a 0-to-1 transition of this bit causes the programmed test pattern (qrss, pts, plf[4:0], ptf[4:0], and bsp[31:0]) to be loaded in to the receive pattern generator. this bit must be changed to 0 and back to 1 for another pattern to be loaded. loading a new pattern forces the receive pattern generator out of the sync state, which causes a resynchronization to be initiated. note: qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four rxck clock cycles after this bit transitions from 0 to 1. bit 4: receive pattern inversion control (rpic). when 0, the receive incoming data stream is not altered. when 1, the receive incoming data stream is inverted. bit 3: manual pattern resynchronization (mpr). a 0-to-1 transition of this bit causes the receive pattern generator to resynchronize to the incoming pattern. this bit must be changed to 0 and back to 1 for another resynchronization to be initiated. note: a manual resynchronization forces the receive pattern generator out of the sync state. bit 2: automatic pattern resynchronization disable (aprd). when 0, the receive pattern generator automatically resynchronizes to the incoming pattern if six or more times during the current 64-bit window the incoming data stream bit and the receive pattern generator output bit did not match. when 1, the receive pattern generator does not automatically resynchronize to the incoming pattern. note: automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the sync state. bit 1: transmit new pattern load (tnpl). a 0-to-1 transition of this bit causes the programmed test pattern (qrss, pts, plf[4:0], ptf[4:0], and bsp[31:0]) to be loaded in to the transmit pattern generator. this bit must be changed to zero and back to one for another pattern to be loaded. note: qrss, pts, plf[4:0}, ptf[4:0], and bsp[31:0] must not change from the time this bit transitions from 0 to 1 until four txck clock cycles after this bit transitions from 0 to 1. bit 0: transmit pattern inversion control (tpic). when 0, the transmit outgoing data stream is not altered. when 1, the transmit outgoing data stream is inverted.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 47 of 97 register name: bpcr1 register description: bert pattern configuration register 1 register address: 02h bit # 7 6 5 4 3 2 1 0 name ? qrss pts plf4 plf3 plf2 plf1 plf0 default 0 0 0 0 0 0 0 0 bit 6: qrss enable (qrss). when 0, the pattern generator configuration is controlled by pts, plf[4:0], and ptf[4:0], and bsp[31:0]. when 1, the pattern generator configuration is forced to a prbs pattern with a generating polynomial of x 20 + x 17 + 1. the output of the pattern generator is forced to one if the next 14 output bits are all 0. bit 5: pattern type select (pts). when 0, the pattern is a prbs pattern. when 1, the pattern is a repetitive pattern. bits 4 to 0: pattern length feedback (plf[4:0]). these bits control the ?length? feedback of the pattern generator. the length feedback is from bit n of the pattern generator (n = plf[4:0] +1). for a prbs signal, the feedback is an xor of bit n and bit y. for a repetitive pattern the feedback is bit n. register name: bpcr 2 register description: bert pattern configuration register 2 register address: 03h bit # 7 6 5 4 3 2 1 0 name ? ? ? ptf4 ptf3 ptf2 ptf1 ptf0 default 0 0 0 0 0 0 0 0 bits 4 to 0: pattern tap feedback (ptf[4:0]). these bits control the prbs ?tap? feedback of the pattern generator. the tap feedback is from bit y of the pattern generator (y = ptf[4:0] +1). these bits are ignored when programmed for a repetitive pattern. for a prbs signal, the feedback is an xor of bit n and bit y.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 48 of 97 register name: bspr1 register description: bert seed/pattern register #1 register address: 04h bit # 7 6 5 4 3 2 1 0 name bsp7 bsp6 bsp5 bsp4 bsp3 bsp2 bsp1 bsp0 default 0 0 0 0 0 0 0 0 register name: bspr2 register description: bert seed/pattern register #2 register address: 05h bit # 7 6 5 4 3 2 1 0 name bsp15 bsp14 bsp13 bsp12 bsp11 bsp10 bsp9 bsp8 default 0 0 0 0 0 0 0 0 register name: bspr3 register description: bert seed/pattern register #3 register address: 06h bit # 7 6 5 4 3 2 1 0 name bsp23 bsp22 bsp21 bsp20 bsp19 bsp18 bsp17 bsp16 default 0 0 0 0 0 0 0 0 register name: bspr4 register description: bert seed/pattern register #4 register address: 07h bit # 7 6 5 4 3 2 1 0 name bsp31 bsp30 bsp29 bsp28 bsp27 bsp26 bsp25 bsp24 default 0 0 0 0 0 0 0 0 bits 31 to 0: bert seed/pattern (bsp[31:0]). these 32 bits are the programmable seed for a transmit prbs pattern, or the programmable pattern for a transmit or receive repetitive pattern. bsp(31) is the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit length prbs. bsp(31) is the first bit input on the receive side for a 32-bit repetitive pattern.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 49 of 97 register name: teicr register description: transmit error-insertion control register register address: 08h bit # 7 6 5 4 3 2 1 0 name ? ? teir2 teir1 teir0 bei tsei meims default 0 0 0 0 0 0 0 0 bits 5 to 3: transmit error-insertion rate (teir[2:0]). these bits indicate the rate at which errors are inserted in the output data stream. one out of every 10 n bits is inverted. teir[2:0] is the value n. a teir[2:0] value of 0 disables error insertion at a specific rate. a teir[2:0] value of 1 result in every 10th bit being inverted. a teir[2:0] value of 2 result in every 100th bit being inverted. error insertion starts when this register is written to with a teir[2:0] value that is non-zero. if this register is written to during the middle of an error insertion process, the new error rate will be started after the next error is inserted. bit 2: bit-error-insertion enable (bei). when 0, single bit-error insertion is disabled. when 1, single bit-error insertion is enabled. bit 1: transmit single error insert (tsei). this bit causes a bit error to be inserted in the transmit data stream if manual error insertion is disabled (meims = 0) and single bit-error insertion is enabled. a 0-to-1 transition causes a single bit error to be inserted. for a second bit error to be inserted, this bit must be set to 0, and back to 1. note: if meims is low, and this bit transitions more than once between error insertion opportunities, only one error is inserted. bit 0: manual-error insert-mode select (meims). when 0, error insertion is initiated by the tsei register bit. when 1, error insertion is initiated by the transmit manual-error-insertion signal (tmei). note: if tmei or tsei is 1, changing the state of this bit may cause a bit error to be inserted. register name: bsr register description: bert status register register address: 0ch bit # 7 6 5 4 3 2 1 0 name ? ? ? ? pms ? bec oos default 0 0 0 0 0 0 0 0 bit 3: performance-monitoring update status (pms). this bit indicates the status of the receive performance- monitoring register (counters) update. this bit transitions from low to high when the update is completed. pms is asynchronously forced low when the lpmu bit (pmum = 0) or rpmu signal (pmum = 1) goes low. bit 1: bit error count (bec). when 0, the bit error count is 0. when 1, the bit error count is 1 or more. bit 0: out of synchronization (oos). when 0, the receive pattern generator is synchronized to the incoming pattern. when 1, the receive pattern generator is not synchronized to the incoming pattern.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 50 of 97 register name: bsrl register description: bert status register latched register address: 0eh bit # 7 6 5 4 3 2 1 0 name ? ? ? ? pmsl bel becl oosl default 0 0 0 0 0 0 0 0 bit 3: performance-monitoring update status latched (pmsl). this bit is set when the pms bit transitions from 0 to 1. a read operation clears this bit. bit 2: bit error latched (bel). this bit is set when a bit error is detected. a read operation clears this bit. bit 1: bit-error count latched (becl). this bit is set when the bec bit transitions from 0 to 1. a read operation clears this bit. bit 0: out-of-synchronization latched (oosl). this bit is set when the oos bit changes state. a read operation clears this bit. register name: bsrie register description: bert status register interrupt enable register address: 10h bit # 7 6 5 4 3 2 1 0 name ? ? ? ? pmsie beie becie oosie default 0 0 0 0 0 0 0 0 bit 3: performance-monitoring update status-interrupt enable (pmsie). this bit enables an interrupt if the pmsl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 2: bit-error-interrupt enable (beie). this bit enables an interrupt if the bel bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 1: bit-error-count interrupt enable (becie). this bit enables an interrupt if the becl bit is set. 0 = interrupt disabled 1 = interrupt enabled bit 0: out-of-synchronization interrupt enable (oosie). this bit enables an interrupt if the oosl bit is set. 0 = interrupt disabled 1 = interrupt enabled
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 51 of 97 register name: rbecr1 register description: receive bit-error-count register #1 register address: 14h bit # 7 6 5 4 3 2 1 0 name bec7 bec6 bec5 bec4 bec3 bec2 bec1 bec0 default 0 0 0 0 0 0 0 0 register name: rbecr2 register description: receive bit-error-count register #1 register address: 15h bit # 7 6 5 4 3 2 1 0 name bec15 bec14 bec13 bec12 bec11 bec10 bec9 bec8 default 0 0 0 0 0 0 0 0 register name: rbecr3 register description: receive bit-error-count register #2 register address: 16h bit # 7 6 5 4 3 2 1 0 name bec23 bec22 bec21 bec20 bec19 bec18 bec17 bec16 default 0 0 0 0 0 0 0 0 bits 23 to 1: bit error count (bec[23:0]). these 24 bits indicate the number of bit errors detected in the incoming data stream. this count stops incrementing when it reaches a count of ff ffffh. the associated bit-error counter is not incremented when an oos condition exists.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 52 of 97 register name: rbcr1 register description: receive bit count register #1 register address: 18h bit # 7 6 5 4 3 2 1 0 name bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 default 0 0 0 0 0 0 0 0 register name: rbcr2 register description: receive bit count register #2 register address: 19h bit # 15 14 13 12 11 10 9 8 name bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 default 0 0 0 0 0 0 0 0 register name: rbcr3 register description: receive bit count register #3 register address: 1ah bit # 7 6 5 4 3 2 1 0 name bc23 bc22 bc21 bc20 bc19 bc18 bc17 bc16 default 0 0 0 0 0 0 0 0 register name: rbcr4 register description: receive bit count register #4 register address: 1bh bit # 15 14 13 12 11 10 9 8 name bc31 bc30 bc29 bc28 bc27 bc26 bc25 bc24 default 0 0 0 0 0 0 0 0 bits 31 to 0: bit count (bc[31:0]). these 32 bits indicate the number of bits in the incoming data stream. this count stops incrementing when it reaches a count of ffff ffffh. the associated bit counter is not incremented when an oos condition exists.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 53 of 97 6 functional description 6.1 power-up and reset internal power_on_reset circuitry generates a reset during power-up. all registers are reset to the default values. writing to the software-reset register generates at least 1 s reset cycle, which has the same effect as the power-up reset. a reset can also be performed in software by writing to swr register. 6.2 master clock the ds26303 requires 2.048mhz 50ppm or 1.544mhz 50ppm or multiple thereof. the receiver uses the mclk as a reference for clock recovery, jitter attenuation, and generating rclk during los. the ais transmission uses mclk for transmit all-ones condition. see register mc to set desired incoming frequency. if the plle bit is not set, mclk is whatever the incoming frequency is. mclk or rclk can also be used to output clka. register ccr is used to select the clock generated for clka and the teclk. any rclk can also be selected as an input to the clock generator using this same register. for a detailed description of selections available, see figure 6-1 . figure 6-1. pre-scaler pll and clock generator pre scaler pll clk gen e1clk t1clk freqs mps1..0 plle pclks2..0 pclki1..0 rlck1..8 plle clka3..0 clkai clka rlos16 clkae teclk rlos1 teclke teclki teclks mclk
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 54 of 97 6.3 transmitter nrz data arrives on tpos and tneg on the transmit system side. the tpos and tneg data is sampled on the falling edge of tclk ( figure 10-12 ). the data is encoded with hdb3 or b8zs or nrz encoding when single-rail mode is selected (only tpos as the data source). when in single-rail mode only, bpv errors can be inserted for test purposes by register beir . preencoded data is expected when dual-rail mode is selected. the encoded data passes through a jitter attenuator if it is enabled for the transmit path. a digital sequencer and dac generate transmit waveforms compliant with t1.102 and g.70 3 pulse masks. a line driver drives an internal matched-impedance circuit for provision of 100 , 110 , 120 , and 75 termination. the ds26303 drivers have short-circuit driver-fail-monitor detection. there is an oe pin that can high-z the transmitter outputs for protection switching. the individual transmitters can be placed in high impedance by register oeb . the ds26303 also has functionality for powering down the transmitters individually. the registers that control the transmitter operation are shown in table 6-3 . table 6-1. telecommunications specification compliance for ds26303 transmitters transmitter function telecommunications compliance ami coding, b8zs substitution, ds1 electrical interface ansi t1.102 t1 telecom pulse mask compliance ansi t1.403 t1 telecom pulse mask compliance ansi t1.102 transmit electrical characteristics for e1 transmission and return loss compliance itut g.703 table 6-2. registers related to control of ds26303 transmitters register name acronym function transmit all-ones enable taoe transmit all-ones enable. driver fault monitor status dfms driver fault status. driver fault monitor interrupt enable dfmie driver fault status interrupt mask. driver fault monitor interrupt status dfmis driver fault status interrupt mask. global configuration register gc selection of the jitter attenuator in the transmit receive or not used and code for b8zs or hdb3 substitution. template select transmitter tst the transmitter that the template select applies to. template select ts the ts2 to ts0 bits for selection of the templates for transmitter and match impedance for the receiver. output enable configuration register oeb this bits can be used to place the transmitter outputs in high- impedance mode. master clock selection mc selects the mclk frequency used for transmit and receive. single-rail mode select register srms this register can be used to select between single-rail and dual-rail mode. line code selection lcs the individual liu line codes can be selected to overwrite the global setting. transmit power-down tpde individual transmitters can be powered down. individual short-circuit-protection disable iscpd this register allows the individual transmitters short-circuit protection disable. bert control register btcr this register is used for sending different bert patterns for the individual transmitters.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 55 of 97 6.3.1 transmit line templates the ds26303 the transmitters can be selected individually to meet the pulse masks for e1 and t1/j1 mode. the t1/j1 pulse mask is shown in the transmit pulse template and can be configured on an individual liu basis. the timprm pin/bit is used to select the internal transmit terminating impedance of 100 /110 for t1/j1 mode or 75 /120 for e1 mode. the t1 pulse mask is shown in figure 6-2 and the e1 pulse template is shown in figure 6-3 . table 6-3. ds26303 template selections ts2, ts1, ts0 application 000 e1 001 010 reserved 011 dsx-1 (0-133 ft) 100 dsx-1 (133-266 ft) 101 dsx-1 (266-399 ft) 110 dsx-1 (399-533 ft) 111 dsx-1 (533-655 ft) figure 6-2. t1 transmit pulse templates 1.2 0 -0 .1 -0 .2 -0 .3 -0 .4 -0 .5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -500 -300 -100 0 300 500 700 -400 -200 200 400 600 100 tim e (ns) norm ali zed am pli tude t1.102/87, t1.403, cb 119 (oct. 79), & i.4 31 t e m p la te -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 ui time amp. maximum curve ui time amp. minimum curve -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.34 0.77 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.20 1.20 1.05 1.05 -0.05 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.61 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.26 -0.05 -0.05 ui time amp. maximum curve ui time amp. minimum curve dsx-1 tem plate (per ansi t1.102 -1993) ds1 tem plate (per ansi t1.403 -1995)
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 56 of 97 figure 6-3 e1 transmit pulse templates 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 time (ns) scaled amplitude 50 100 150 200 250 -50 -100 -150 -200 -250 269ns 194ns 219ns (in 75 ohm systems, 1.0 on the scale = 2.37vpeak in 120 ohm systems, 1.0 on the scale = 3.00vpeak) g.703 template
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 57 of 97 6.3.2 liu transmit front end it is recommended to configure the transmitter?s liu as described in figure 6-4 and in table 6-4 . no series resistors are required. the transmitter has internal termination for e1, j1, and t1 modes. figure 6-4. liu front end c1 ds26303 (one channel) ttip tring rtip rring dt dt dt dt ct 1:2 tft 1:2 tfr tx line rx line tvddn tvssn tvs1 3.3v c2 3.3v c3 avddn avssn 3.3v c4 rt c5 rt 30 a110 a100 a75 table 6-4. liu front-end values mode component 75 coax 120 twisted pair 100 /110 twisted pair tx capacitance ct 560pf typical. adjust for board parasitics for optimal return loss. tx protection dt international rectifier: 11dq04 or 10bq060 motorola: mbr0540t1 rx transformer 1:2 tfr tx transformer 1:2 tft pulse: t1124 (0c to +70c) pulse: t1114 (-40c to +85c) tx decoupling (atvdd) c1 common decoupling for all eight channels is 68 f. tx decoupling (atvdd) c2 recommended decoupling per channel is 0.1 f. rx decoupling (avddn) c3 common decoupling for all eight channels is 68 f. rx decoupling (avddn) c4 common decoupling for all eight channels is 0.1 f. rx termination c5 when in external impedance mode, rx capacitance for all eight channels is 0.1 f. do not populate if using internal impedance mode. rx termination rt when in external impedance mode, the two resistors for all modes are 15.0 1%. do not populate if using internal impedance mode. voltage protection tvs1 sgs-thomson: smlvt 3v3 (3.3v transient suppressor)
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 58 of 97 6.3.3 dual-rail mode dual-rail mode consists of tpos, tneg, and tclk pins on the system side. nrz data is sampled on the falling edge of tclk as shown in figure 10-12 . the zero substitution b8zs or hdb3 is not allowed. the tpos/tneg data is encoded in ami format on the ttip and tring pins. the data that appears on the tpos pin is output on ttip and data on the tring is output on tring after pulse shaping. the single-rail-select register ( srms ) is used for selection of dual-rail or single-rail mode. the data that arrives at the tpos and tneg can be overwritten in the maintenance mode by setting the bert control register ( btcr ). 6.3.4 single-rail mode single-rail mode consists of tpos, tneg, and tclk pins on the system side. nrz data is sampled on the falling edge of tclk as shown in figure 10-12 . the zero substitution b8zs or hdb3 is allowed. the tpos data is encoded in ami format on the ttip and tring pins after pulse shaping. the single-rail-mode select ( srms ) is used for selection of dual-rail or single-rail mode. the data that arrives at the tpos can be overwritten in the maintenance mode by setting in bert control register ( btcr ). 6.3.5 zero suppression?b8zs or hdb3 b8zs coding is available when the device is in t1 mode selected by the ts2, ts1, and ts0 bits in the ts register. setting the lcs bit in the lcs register enables b8zs. note that if the individual liu is configured in e1 mode, then hdb3 code substitution can be selected. bipolar violations can be inserted via the tneg/bpvi pin or transmit maintenance register settings only if b8zs or hdb3 coding is turned off. b8zs substitution is defined in ansi t1.102 and hdb3 in itut g.703 standards. 6.3.6 transmit power-down the transmitter is powered down if the relevant bits in the tpde register are set. 6.3.7 transmit all ones when transmit all ones is invoked, continuous 1s are transmitted using mclk as the timing reference. data input at tpos and tneg is ignored. transmit all ones can be sent by setting bits in the taoe register. transmit all ones are enabled if bits in register ataos are set and the corresponding receiver goes into an los state in the status register loss . 6.3.8 drive failure monitor the driver fail monitor is connected to the ttip and tring pins. it will detect a short circuit on the secondary side of the transmit transformer. the drive current will be limited to 50 ma if a short circuit is detected. the dfms status registers and the corresponding interrupt and enable registers can be used to monitor the driver failure. 6.4 receiver the ds26303?s eight receivers are all identical. a 2:1 transformer steps down the input from the line. the ds26303 is designed to be fully software-selectable for e1 and t1/j1 without the need to change any external resistors for the receive side. the output of the internal termination circuitry is fed into a peak detector. the peak detector and data slicer process the received signal. the output of the data slicer goes to clock and data recovery. a 2.048/1.544 pll is internally multiplied by 8 by another internal pll and fed to the clock recovery system derives e1 or t1 clock. the clock-recovery system uses the clock from the pll circuit to form an 8-times oversampler, which is used to recover the clock and data. this oversampling technique offers outstanding performance to meet jitter tolerance specifications. depending on selection options, b8zs/hdb3/ami decoding is performed. these decoded data is provided to the system side in either single-rail or dual-rail mode. the selection of single rail or dual rail is done by settings in the srms register. 6.4.1 peak detector and slicer the slicer determines the polarity and presence of the received data. the output of the slicer is sent to the clock and data recovery circuitry for extraction of data and clock. the slicer has a built-in peak detector for determination of the slicing threshold.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 59 of 97 6.4.2 clock and data recovery the resultant e1 or t1 clock derived from the 2.048/1.544 pll (jaclk in) is internally multiplied by 16 by another internal pll and fed to the clock recovery system. the clock recovery system uses the clock from the pll circuit to form a 16-times oversampler, which is used to recover the clock and data. this oversampling technique offers outstanding performance to meet jitter tolerance specifications. 6.4.3 loss of signal the ds26303 uses both the digital and analog loss-detection method in compliance with the latest t1.231 for t1/j1 and itu g.775 or etsi 300 233 for e1 mode of operation. los is detected if the receiver level falls bellow a threshold analog voltage for a certain duration. alternatively, this can be termed as having received zeros for a certain duration. the signal level and timing duration are defined in accordance with the t1.231 or g.775 or etsi 300 233 specifications. the loss-detection thresholds are based on cable loss of 15db for both t1 and e1 mode. rclk is replaced by mclk when the receiver detects a loss of signal if the aisel bit is set in the gc register, or if the iaisel .ilaise bit is set. the rpos/rneg data is replaced by an all-ones signal upon receiving an los to indicate ais to the downstream device. the loss state is exited when the receiver detects a certain number of ones density at a higher signal level than the loss-detection level. the loss-detection-signal level and loss-reset-signal level are defined with a hysteresis to prevent the receiver from bouncing between los and no-los states. the following table outlines the specifications governing the loss function. table 6-5. loss criteria t1.231, g.775, and etsi 300 233 specifications standard criteria t1.231 itu g.775 etsi 300 233 loss detection no pulses are detected for 175 75 bits. no pulses are detected for duration of 10 to 255 bit periods. no pulses are detected for a duration of 2048 bit periods or 1ms, loss reset loss is terminated if a duration of 12.5% ones are detected over duration of 175 75 bits. loss is not terminated if eight consecutive 0s are found if b8zs encoding is used. if b8zs is not used, loss is not terminated if 100 consecutive pulses are 0. the incoming signal has transitions for duration of 10 to 255 bit periods. loss reset criteria is not defined. 6.4.3.1 ansi t1.231 for t1 and j1 modes loss is detected if the received signal level is less than 200mv for duration of 192 bit periods. los is reset if the all of the following criteria are met: 24 or more 1s are detected in a 192-bit period with a detection threshold of 300mv measured at rtip and rring. during the 192 bits less than 100 consecutive zeros are detected. eight consecutive 0s are not detected if b8zs is set. 6.4.3.2 itu g.775 for e1 modes los is detected if the received signal level is less than 200mv for a continuous duration of 192 bit periods. los is reset if the receive signal level is greater than 300mv for a duration of 192 bit periods. 6.4.3.3 etsi 300 233 for e1 modes los is detected if the received signal level is less than 200mv for a continuous duration of 2048 (1ms) bit periods. los is reset if the receive signal level is greater than 300mv for a duration of 192 bit periods.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 60 of 97 6.4.4 ais table 6-6 outlines the ds26303 ais-related specifications. table 6-7 states the ais functionality in the ds26303. the registers related to the ais detection are shown in table 6-8 . table 6-6. ais criteria t1.231, g.775, and etsi 300 233 specifications standard criteria itu g.775 for e1 etsi 300233 for e1 ansi t1.231 for t1 ais detection two or fewer 0s in each of two consecutive 512-bit streams received. fewer than three 0s detected in 512-bit period. fewer than nine 0s detected in a 8192-bit period (a ones density of 99.9% over a period of 5.3ms) are received. ais clearance three or more 0s in each of two consecutive 512-bit streams received. three or more 0s in a 512-bit period received. nine or more 0s detected in a 8192-bit period are received. table 6-7. ais detection and reset criteria standard criteria itu g.775 for e1 etsi 300233 for e1 ansi t1.231 for t1 ais detection two or fewer 0 in each of two consecutive 512-bit streams received. fewer than three 0s detected in 512-bit period. fewer than nine 0s contained in 8192 bits. ais clearance three or more 0s in each of two consecutive 512-bit streams received. three or more 0s in a 512-bit period received. nine or more bits received in a 8192-bit stream. table 6-8. registers related to ais detection register acronym pointer functionality los/ais criteria lascs section criteria for ais. t1.231, g.775, etsi 300233 for e1. ais register ais set when ais is detected. ais enable register aisie if reset interrupt due to ais is not generated. ais interrupt aisi latched if there is a change in ais and the interrupt is enabled.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 61 of 97 6.4.5 bipolar violation and excessive zero detector the ds26303 detects code violations, bpv, and excessive zero errors. the reporting of the errors is done through the pin rnegn/cvn. excessive zeros are detected if eight consecutive 0s are detected with b8zs enabled and four consecutive 0s are detected with hdb3 enabled. excessive zero detection is selectable when single-rail mode and hdb3/b8zs encoding/decoding is selected. the bits in ezde and cvdeb registers determine the combinations that are reported. table 6-9 outlines the functionality: table 6-9. bpv, code violation, and excessive zero error reporting conditions cvn pin reports ezde is reset, cvdeb is reset bpv + code violation ezde is set, cvdeb is reset bpv + code violation + excessive zero ezde is reset, cvdeb is set bpv ezde is set, cvdeb is set bpv + excessive zero 6.4.6 liu receiver front end it is recommended that the receiver be configured as per table 6-4 and figure 6-4 . internal or external mode for the receiver front end can be selected by register gc.rimpms . when this bit is set to external mode the user is required to supply two 15 resistors as shown in figure 6-4 . the internal adjust resistors a75, a100, and a110 will still be set in external mode if 75 , 100 , or 110 impedance is selected during template selection. however, the internal 30 resistor will be disconnected. if the user would like all the adjust resistors to be disconnected or any internal impedance matching, then the user should set the ts.rimpoff bit for each liu or the rimpoff pin when in hardware mode. 6.5 hitless-protection switching (hps) many current redundancy protection implementations use mechanical relays to switch between primary and backup boards. the switching time in relays is typically in the milliseconds, making t1/e1 hps impossible. the switching event likely causes frame-synchronization loss in any equipment downstream, affecting the quality of service. the same is also true for tri-stating mechanisms that use software or inactive clocks for the triggering of hps. the ds26303 liu includes fast tri-statable outputs for ttip and tring and fast turn-off impedance matching for the rtip and rring within less than one bit cycle. the control logic is shown in figure 6-5 . in software mode, the user can set the rhpmc bit, which allows the oe pin to control both the transmitter outputs and the receive impedance matching. this is a very useful function in that control can be done through a hardware pin, allowing a quick switch to the backup system for both the receiver and the transmitter. figure 6-6 shows a typical hps application in software mode where the oe is used for control. in hardware mode, the receiver can have impedance matching turned off quickly by using the rimpoff pin, and the transmitter output can be turned off quickly by using the oe pin.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 62 of 97 figure 6-5. hps logic q q set clr d q q set clr d q q set clr d oe rimpoff oeb rimpoff rhpmc hw/sw mode rint_imp_off int_oe_off figure 6-6. hps block diagram primary board backup board switching control oe oe tring rtip ttip rring tring rtip ttip rring line interface card rx tx
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 63 of 97 6.6 jitter attenuator the ds26303 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits by the jads bit in register gc . it can also be controlled on an individual liu basis by settings in the ijafds register. the 128- bit mode is used in applications where large excursions of wander are expected. the 32-bit mode is used in delay- sensitive applications. the characteristics of the attenuation are shown in figure 6-7 . the jitter attenuator can be placed in either the receive path or the transmit path or none by appropriately setting the japs and the jae bits in register gc . these selections can be changed on an individual liu basis by settings in the ijaps and ijae . for the jitter attenuator to properly operate, a 2.048mhz or multiple thereof, or 1.544mhz clock or multiple thereof must be applied at mclk. itu specification g.703 requires an accuracy of 50ppm for both t1 and e1 applications. tr62411 and ansi specs require an accuracy of 32ppm for t1 interfaces. on-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the tclk pin to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator fifo. it is acceptable to provide a gapped/bursty clock at the tclk pin if the jitter attenuator is placed on the transmit side. if the incoming jitter exceeds either 120ui p-p (buffer depth is 128 bits) or 28ui p-p (buffer depth is 32 bits), then the ds26303 divides the internal nominal 32.768mhz (e1) or 24.704mhz (t1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. when the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (jflt) bits in the ijaflt register described. figure 6-7. jitter attenuation frequency (hz) 0db -20db -40db -60db 1 10 100 1k 10k jitter attenuation (db) 100k tr 62411 (dec. 90) prohibited area c u r v e b curve a itu g.7xx prohibited area tbr12 prohibited area t1 e1
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 64 of 97 6.7 g.772 monitor in this application, only seven lius are functional and one liu is used for nonintrusive monitoring of input and output of the other seven channels. channel 1 is used for monitoring channels 2 to 8. g.772 monitoring is configured by the gmc register (see table 5-9 ). while monitoring with channel 1, the device can be configured in remote loopback and the monitored signal can be output on ttip1 and tring1. 6.8 loopbacks the ds26303 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote loopback, and dual loopback. 6.8.1 analog loopback the analog output of the transmitter ttip and tring is looped back to rtip and rring of the receiver. data at rtip and rring is ignored in analog loopback. see figure 6-8 . figure 6-8. analog loopback line driver hdb3/ b8zs e ncoder o ptional jitter a ttenuator transm it digital transm it analog tclk tpos tneg hdb3/ b8zs d ecoder o ptional jitter a ttenuator receive digital receive analog rclk rpos rneg rtip rring 6.8.2 digital loopback the transmit system data tpos, tneg, and tclk are looped back to output on rclk, rpos, and rneg. the data input at tpos and tneg is encoded and output on ttip and tring. signals at rtip and rring are ignored. this loopback is conceptually shown in figure 6-9 .
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 65 of 97 figure 6-9. digital loopback line driver hdb3/ b8zs e ncoder o ptional jitter a ttenuator transm it digital transm it analog tclk tpos tneg hdb3/ b8zs d ecoder o ptional jitter a ttenuator receive digital receive analog rclk rpos rneg rtip rring tpos tneg 6.8.3 remote loopback the inputs at rtip and rring are looped back to ttip and tring. the inputs at tclk, tpos, and tneg are ignored during a remote loopback. this loopback is conceptually shown in figure 6-10 . figure 6-10. remote loopback line driver hdb3/ b8zs e ncoder o ptional jitter a ttenuator transm it digital transm it analog tclk tpos tneg hdb3/ b8zs d ecoder o ptional jitter a ttenuator receive digital receive analog rclk rpos rneg rtip rring tpos tneg
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 66 of 97 6.9 bert the bert is a software-programmable test-pattern generator and monitor capable of meeting most error- performance requirements for digital transmission equipment. it generates and synchronizes to pseudorandom patterns with a generation polynomial of the form x n + x y + 1, where n and y can take on values from 1 to 32 and to repetitive patterns of any length up to 32 bits. the transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data stream. the receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern. the features include: programmable prbs pattern. the pseudorandom bit sequence (prbs) polynomial (x n + x y + 1) and seed are programmable (length n = 1 to 32, tap y = 1 to n ? 1, and seed = 0 to 2 n ? 1). programmable repetitive pattern. the repetitive pattern length and pattern are programmable (the length n = 1 to 32 and pattern = 0 to 2 n ? 1). 24-bit error count and 32-bit bit count registers programmable bit-error insertion. errors can be inserted individually, on a pin transition, or at a specific rate. the rate 1/10 n is programmable (n = 1 to 7). pattern synchronization at a 10 -3 ber. pattern synchronization is achieved even in the presence of a random bit-error rate (ber) of 10 -3 . 6.9.1 configuration and monitoring set port.cr1 .bena = 1 to enable the bert. the following tables show how to configure the on-board bert to send and receive common patterns. table 6-10. pseudorandom pattern generation bpcr register bert.cr pattern type ptf[4:0] (hex) plf[4:0] (hex) pts qrss bert. pcr bert. spr2 bert. spr1 tpic, rpic 2 9 -1 o.153 (511 type) 04 08 0 0 0x0408 0xffff 0xffff 0 2 11 -1 o.152 and o.153 (2047 type) 08 0a 0 0 0x080a 0xffff 0xffff 0 2 15 -1 o.151 0d 0e 0 0 0x0d0e 0xffff 0xffff 1 2 20 -1 o.153 10 13 0 0 0x1013 0xffff 0xffff 0 2 20 -1 o.151 qrss 02 13 0 1 0x0253 0xffff 0xffff 0 2 23 -1 o.151 11 16 0 0 0x1116 0xffff 0xffff 1 table 6-11. repetitive pattern generation bpcr register pattern type ptf[4:0] (hex) plf[4:0] (hex) pts qrss bert. pcr bert. spr2 bert. spr1 all 1s na 00 1 0 0x0020 0xffff 0xffff all 0s na 00 1 0 0x0020 0xffff 0xfffe alternating 1s and 0s na 01 1 0 0x0021 0xffff 0xfffe double alternating and 0s na 03 1 0 0x0023 0xffff 0xfffc 3 in 24 na 17 1 0 0x0037 0xff20 0x0022 1 in 16 na 0f 1 0 0x002f 0xffff 0x0001 1 in 8 na 07 1 0 0x0027 0xffff 0xff01 1 in 4 na 03 1 0 0x0023 0xffff 0xfff1
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 67 of 97 after configuring these bits, the pattern must be loaded into the bert. this is accomplished through a 0-to-1 transition on bcr .tnpl and bcr .rnpl monitoring the bert requires reading the bsr register that contains the bec bit and the oos bit. the bec bit is 1 when the bit-error counter is 1 or more. the oos is 1 when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64-bit window. the receive bert bit-count register ( rbcr ) and the receive bert bit-error count register ( rbecr ) are updated upon the reception of a performance-monitor update signal (e.g., bcr . lpmu). this signal updates the registers with the values of the counters since the last update and resets the counters. 6.9.2 receive pattern detection the receive bert receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. the receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output is forced to 1 if the next 14 bits are all 0s. qrss is programmable (on or off). for prbs and qrss patterns, the feedback is forced to 1 if bits 1 through 31 are all 0s. depending on the type of pattern programmed, pattern detection performs either prbs synchronization or repetitive pattern synchronization. 6.9.2.1 receive prbs synchronization prbs synchronization synchronizes the receive pattern generator to the incoming prbs or qrss pattern. the receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern re-synchronization is initiated. automatic pattern resynchronization can be disabled. refer to figure 6-11 for the prbs synchronization diagram. figure 6-11. prbs synchronization state diagram sync load verify 1 bit error 32 bits loaded 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 68 of 97 6.9.2.2 receive repetitive pattern synchronization repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. the receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. synchronization is achieved if all 32 bits match the incoming pattern. if at least six incoming bits in the current 64-bit window do not match the receive prbs pattern generator, automatic pattern resynchronization is initiated. automatic pattern resynchronization can be disabled. see figure 6-12 for the repetitive pattern synchronization state diagram. figure 6-12. repetitive pattern synchronization state diagram sync match verify 1 bit error pattern matches 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s 6.9.2.3 receive pattern monitoring receive pattern monitoring monitors the incoming data stream for both an oos condition and bit errors and counts the incoming bits. an out-of-synchronization (oos) condition is declared when the synchronization state machine is not in the sync state. an oos condition is terminated when the synchronization state machine is in the sync state. bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. if they do not match, a bit error is declared, and the bit error and bit counts are incremented. if they match, only the bit count is incremented. the bit count and bit-error count are not incremented when an oos condition exists. 6.9.3 transmit pattern generation pattern generation generates the outgoing test pattern and passes it onto error insertion. the transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (lsb) or bit 1 to the most significant bit (msb) or bit 32. the input to bit 1 is the feedback. for a prbs pattern (generating polynomial x n + x y + 1), the feedback is an xor of bit n and bit y. for a repetitive pattern (length n), the feedback is bit n. the values for n and y are individually programmable (1 to 32). the output of the receive pattern generator is the feedback. if qrss is enabled, the feedback is an xor of bits 17 and 20, and the output will be forced to one if the next 14 bits are all 0s. qrss is programmable (on or off). for prbs and qrss patterns, the feedback will be forced to 1 if bits 1 to 31
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 69 of 97 are all 0s. when a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern generation starts. the seed/pattern value is programmable (0 ? 2 n ? 1). 6.9.3.1 transmit error insertion error insertion inserts errors into the outgoing pattern data stream. errors are inserted one at a time or at a rate of one out of every 10 n bits. the value of n is programmable (1 to 7 or off). single bit-error insertion can be initiated from the microprocessor interface, or by the manual error-insertion input (tmei). the method of single error insertion is programmable (register or input). if pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. pattern inversion is programmable (on or off). 6.10 special test functions this section is used for designer notes. any special features or test functions that are for internal use or possible future features that may be needed should be documented here. 6.10.1 metal options the ds26303 has a metal option to allow for pins d0 to d7 to be metal revised. the metal revision adds vddio/2 pullup and pulldown to pins d0 to d7. this has been added in case compatibility in hardware mode needs to match the lxt384 part.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 70 of 97 7 jtag boundary scan architecture and test access port the ds26303 ieee 1149.1 design supports the standard instruction codes sample/preload, bypass, and extest. optional public instructions included are highz, clamp, and idcode. the ds26303 contains the following as required by ieee 1149.1 standard test access port and boundary scan architecture: test access port (tap) tap controller instruction register bypass register boundary scan register device identification register details on boundary scan architecture and the test access port can be found in ieee 1149.1-1990, ieee 1149.1a-1993, and ieee 1149.1b-1994. the test access port has the necessary interface pins: jtrstb, tclk, jtms, jtdi, and jtdo. see the pin descriptions for details. for the latest bsdl file go to www.maxim-ic.com/tools/bsdl/ and search for ds26303. figure 7-1. jtag functional block diagram +v instruction register jtd1 jtms tclk jtrstb jtdo +v +v test access port controller mux 10k 10k select output enable 10k bypass register identification register boundary scan register
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 71 of 97 7.1 tap controller state machine the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of tclk. the state diagram is shown in figure 7-2 . test-logic-reset upon power-up, the tap controller will be in the test-logic-reset state. the instruction register will contain the idcode instruction. all system logic of the device will operate normally. this state is automatically entered during power up. this state is entered from any state if the jtms is held high for at least 5 clocks. run-test-idle the run-test-idle is used between scan operations or during specific tests. the instruction register and test registers will remain idle. the controller remains in this state when jtms is held low. when the jtms is high and rising edge of tclk is applied the controller moves to the select-dr-scan state. select-dr-scan all test registers retain their previous state. with jtms low, a rising edge of tclk moves the controller into the capture-dr state and will initiate a scan sequence. jtms high during a rising edge on tclk moves the controller to the select-ir-scan state. capture-dr data can be parallel-loaded into the test-data registers if the current instruction is extest or sample/preload. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. on the rising edge of tclk, the controller will go to the shift-dr state if jtms is low or it will go to the exit1-dr state if jtms is high. shift-dr the test-data register selected by the current instruction will be connected between jtdi and jtdo and will shift data one stage towards its serial output on each rising edge of tclk. if a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. when the tap controller is in this state and a rising edge of tclk is applied, the controller enters the exit1-dr state if jtms is high or remains in shift- dr state if jtms is low. exit1-dr while in this state, a rising edge on tclk will put the controller in the update-dr state, which terminates the scanning process, if jtms is high. a rising edge on tclk with jtms low will put the controller in the pause-dr state. pause-dr shifting of the test registers is halted while in this state. all test registers selected by the current instruction will retain their previous state. the controller will remain in this state while jtms is low. a rising edge on tclk with jtms high will put the controller in the exit2-dr state. exit2-dr a rising edge on tclk with jtms high while in this state will put the controller in the update-dr state and terminate the scanning process. a rising edge on tclk with jtms low will enter the shift-dr state.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 72 of 97 update-dr a falling edge on tclk while in the update-dr state will latch the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. select-ir-scan all test registers retain their previous state. the instruction register will remain unchanged during this state. with jtms low, a rising edge on tclk moves the controller into the capture-ir state and will initiate a scan sequence for the instruction register. jtms high during a rising edge on tclk puts the controller back into the test-logic- reset state. capture-ir the capture-ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of tclk. if jtms is high on the rising edge of tclk, the controller will enter the exit1- ir state. if jtms is low on the rising edge of tclk, the controller will enter the shift-ir state. shift-ir in this state, the shift register in the instruction register is connected between jtdi and jtdo and shifts data one stage for every rising edge of tclk towards the serial output. the parallel registers as well as all test registers remain at their previous states. a rising edge on tclk with jtms high will move the controller to the exit1-ir state. a rising edge on tclk with jtms low will keep the controller in the shift-ir state while moving data one stage thorough the instruction shift register. exit1-ir a rising edge on tclk with jtms low will put the controller in the pause-ir state. if jtms is high on the rising edge of tclk, the controller will enter the update-ir state and terminate the scanning process. pause-ir shifting of the instruction shift register is halted temporarily. with jtms high, a rising edge on tclk will put the controller in the exit2-ir state. the controller will remain in the pause-ir state if jtms is low during a rising edge on tclk. exit2-ir a rising edge on tclk with jtms high will put the controller in the update-ir state. the controller will loop back to shift-ir if jtms is low during a rising edge of tclk in this state. update-ir the instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of tclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on tclk with jtms low will put the controller in the run-test-idle state. with jtms high, the controller will enter the select-dr-scan state.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 73 of 97 figure 7-2. tap controller state diagram 1 0 0 1 11 1 1 1 1 1 11 1 1 00 0 0 0 1 0 0 0 0 1 1 0 0 0 0 select dr-scan capture dr shift dr exit dr pause dr exit2 dr update dr select ir-scan capture ir shift ir exit ir pause ir exit2 ir update ir test logic reset run test/ idle 0
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 74 of 97 7.2 instruction register the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift-ir state, the instruction shift register will be connected between jtdi and jtdo. while in the shift-ir state, a rising edge on tclk with jtms low will shift the data one stage towards the serial output at jtdo. a rising edge on tclk in the exit1-ir state or the exit2-ir state with jtms high will move the controller to the update-ir state. the falling edge of that same tclk will latch the data in the instruction shift register to the instruction parallel output. instructions supported by the ds26303 and its respective operational binary codes are shown in table 7-1 . table 7-1. instruction codes for ieee 1149.1 architecture instruction selected regi ster instruction codes extest boundary scan 000 highz bypass 010 clamp bypass 011 sample/preload boundary scan 100 idcode device identification 110 bypass bypass 111 extest this allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via the update-ir state, the parallel outputs of all digital output pins will be driven. the boundary scan register will be connected between jtdi and jtdo. the capture-dr will sample all digital inputs into the boundary scan register. highz all digital outputs of the device will be placed in a highz state. the bypass register will be connected between jtdi and jtdo. clamp all digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between jtdi and jtdo. the outputs will not change during the clamp instruction. sample/preload this is a mandatory instruction for the ieee 1149.1 specification that supports two functions. the digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-dr state. sample/preload also allows the device to shift data into the boundary scan register via jtdi using the shift-dr state. idcode when the idcode instruction is latched into the parallel instruction register, the identification test register is selected. the device identification code will be loaded into the identification register on the rising edge of tclk following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially via jtdo. during test-logic-reset, the identification code is forced into the instruction register?s parallel output. the id code will always have a 1 in the lsb position. the next 11 bits identify the manufacturer?s jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version table 7-2 . table 7-3 lists the device id code for the ds26303. bypass when the bypass instruction is latched into the parallel instruction register, jtdi connects to jtdo through the one-bit bypass test register. this allows data to pass from jtdi to jtdo not affecting the device?s normal operation.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 75 of 97 table 7-2. id c ode structure msb lsb version contact factory device id jedec 1 4 bits 16 bits 00010100001 1 table 7-3 device id codes part die rev jtag rev jtag id ds26303-075 a1 0h 0080h ds26303-125 a1 0h 0081h 7.3 test registers ieee 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. an optional test register has been included with the ds26303 design. this test register is the identification register and is used with the idcode instruction and the test-logic-reset state of the tap controller. 7.3.1 boundary scan register this register contains both a shift register path and a latched parallel output for all control cells and digital i/o cells and is n bits in length. 7.3.2 bypass register this is a single 1-bit shift register used with the bypass, clamp, and highz instructions that provide a short path between jtdi and jtdo. 7.3.3 identification register the identification register contains a 32-bit shift register and a 32-bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in the test-logic-reset state. see table 7-2 and table 7-3 for more information about bit usage.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 76 of 97 8 operating parameters absolute maximum ratings voltage range on any lead with respect to v ss (except v dd )?????????????????.-0.3v to +5.5v supply voltage (v dd ) range with respect to v ss ???..???????????????????-0.3v to +3.63v operating temperature range for ds26303g/ds26303l?...?????????????????...0c to +70c operating temperature range for ds26303gn/ds26303ln.?????????????????-40c to +85c storage temperature??????????????????????????????????-55c to +125c soldering temperature??????????????????????.see ipc/jedec j-std-020 specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. table 8-1. recommended dc operating conditions (t a = -40c to +85c for ds26303gn and ds26303ln.) parameter symbol conditions min typ max units 2 logic 1 v ih (note 1) 2/3v dd + 0.2 5.5 v 0.8 logic 0 v il (note 1) -0.3 1/3v dd - 0.2 v midrange level (note 1) 1/3v dd + 0.2 1/2 x v dd 2/3v dd - 0.2 v supply voltage v dd 3.135 3.3 3.465 v note 1: applies to pins lp1?lp8, jas, and modesel. table 8-2. capacitance (t a = +25c) parameter symbol conditions min typ max units input capacitance c in 7 pf output capacitance c out 7 pf table 8-3. dc characteristics (v dd = 3.135v to 3.465v, t a = -40c to +85c.) parameter symbol conditions min typ max units 3.465v (notes 1, 2) 478 supply current i dd 3.3v 250 ma input leakage i il ?10.0 +10.0 a tri-state output leakage i ol ?10.0 +10.0 a output voltage (i o = ?4.0ma) v oh 2.4 v output voltage (i o = +4.0ma) v ol 0.4 v note 1: rclk1-n = tclk1-n = 1.544mhz. note 2: power dissipation with all ports active, ttip and tring driving a 25 load, for an all-ones data density.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 77 of 97 9 thermal characteristics table 9-1. thermal characteristics parameter min typ max units power dissipation with rimpms = 0 (notes 1, 2) 0.7 1.40 w power dissipation with rimpms = 1(notes 1, 2) 0.9 1.65 w ambient temperature (note 3) -40 +85 c junction temperature +125 c +21.3 (note 4) theta-ja ( ja ) in still air for 144-pin elqfp 29.0 (note 5) c/w note 1: rclk1-n = tclk1-n = 1.544mhz. note 2: power dissipation with all ports active, ttip and trin driving a 25 load, for an all-ones data density. note 3: the package is mounted on a four-layer jedec standard test board. note 4: theta-ja ( ja ) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer jedec standard test board and the die attach pad is soldered to the test board. note 5: theta-ja ( ja ) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer jedec standard test board and the die attach pad is not soldered to the test board.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 78 of 97 10 ac characteristics 10.1 line interface characteristics table 10-1. transmitter characteristics parameter symbol conditions min typ max units e1 75 2.14 2.37 2.6 e1 120 2.7 3.0 3.3 t1 100 2.4 3.0 3.6 output mark amplitude v t1 110 2.4 3.0 3.6 v output zero amplitude (note 1) v s -0.3 +0.3 v transmit amplitude variation with supply -1 +1 % single rail 8 transmit path delay dual rail 3 ui table 10-2. receiver characteristics parameter symbol conditions min typ max units cable attenuation attn 12 db (note 1) 200 analog loss-of-signal threshold hysteresis short-haul mode 100 mv 192 192 allowable zeros before loss (note 2) 2048 24 192 allowable ones before loss (note 3) 192 dual rail 3 receive path delay single rail 8 ui note 1: measured at the rring and rtip pins. note 2: 192 zeros for t1 and t1.231 specification compliance. 192 zeros for e1 and g.775 specification compliance. 2048 zeros for etsi 300 233 compliance. note 3: 24 ones in 192-bit period for t1.231. 192 ones for g.775, 192 ones for etsi 300 233.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 79 of 97 10.2 parallel host interface timing characteristics table 10-3. intel read mode characteristics (v dd = 3.3v 5%, tj = -40c to +125c.) ( figure 10-1 and figure 10-2 ) signal name(s) symbol description (note 1) min typ max units rdb t1 pulse width 60 ns csb t2 setup time to rdb 0 ns csb t3 hold time from rdb 0 ns ad[7:0] t4 setup time to ale 10 ns a[5:0] t5 hold time from rdb 0 ns d[7:0], ad[7:0] t6 delay time rdb, csb active 6 48 ns d[7:0], ad[7:0] t7 deassert delay from rdb, csb inactive 3 35 ns rdyb t8 enable delay time from csb active 0 12 ns rdyb t9 disable delay time from the csb inactive 12 ns a[5:0] t10 setup time to rdb active 6 ns ale t11 pulse width 10 ns a[5:0] t12 hold time from ale 5 ns rdb t13 output delay time of ad[7:0], d[7:0] 10 50 ns rdyb t14 delay time from rdb inactive 0 12 ns rdyb t15 active output delay time from rdb 40 52 ns ale t16 inactive time to rdb active 2 ns note 1: the input/output timing reference level for all signals is v dd /2.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 80 of 97 figure 10-1. intel nonmuxed read cycle a[5:0] rdb csb d[7:0] rdy ale=(1) address data out t1 t10 t3 t7 t15 t8 t5 t9 t2 t6 t14 t13
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 81 of 97 figure 10-2. intel mux read cycle rdb csb ad[7:0] rdy ale address data out t1 t13 t3 t7 t15 t8 t9 t2 t6 t14 t11 t12 t4 t16
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 82 of 97 table 10-4. intel write cycle characteristics (v dd = 3.3v 5%, tj = -40c to +125c.) ( figure 10-3 and figure 10-4 ) signal name(s) symbol description (note 1) min typ max units wrb t1 pulse width 60 ns csb t2 setup time to wrb 0 ns csb t3 hold time to wrb 0 ns ad[7:0] t4 setup time to ale 10 ns a[5:0] t5 hold time from wrb inactive 2 ns d[7:0], ad[7:0] t6 input setup time to wrb inactive 40 ns d[7:0], ad[7:0] t7 input hold time to wrb inactive 30 ns rdyb t8 enable delay from csb active 0 13 ns rdyb t9 delay time from wrb active 40 ns rdyb t10 delay time from wrb inactive 0 12 ns rdyb t11 disable delay time from csb inactive 12 ns ale t12 pulse width 10 ns ale t13 inactive time to wrb active 10 ns a[5:0] t14 hold time from ale inactive 10 ns a[5:0] t15 setup time to wrb inactive 17 ns note 1: the input/output timing reference level for all signals is v dd /2.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 83 of 97 figure 10-3. intel nonmux write cycle a[5:0] wrb csb d[7:0] rdy ale=(1) address write data t1 t 1 5 t 3 t 7 t9 t5 t 1 1 t2 t6 t10 t8
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 84 of 97 figure 10-4. intel mux write cycle wrb csb ad[7:0] rdy ale address write data t1 t3 t7 t9 t8 t11 t2 t10 t12 t14 t4 t6 t13
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 85 of 97 table 10-5. motorola read cycle characteristics (v dd = 3.3v 5%, tj = -40c to +125c.) ( figure 10-5 and figure 10-6 ) signal name(s) symbol description min typ max units ds t1 pulse width (note 1) 60 ns csb t2 setup time to dsb active (note 1) 0 ns csb t3 hold time from dsb inactive (note 1) 0 ns rwb t4 setup time to dsb active (note 1) 10 ns rwb t5 hold time from dsb inactive (note 1) 0 ns ad[7:0] t6 setup time to asb/dsb active (notes 1, 2) 10 ns ad[7:0] t7 hold time from asb/dsb active (notes 1, 2) 5 ns ad[7:0], d[7:0] t8 output valid delay time from dsb active (note 1) 3 30 ns ad[7:0], d[7:0] t9 invalid output delay time from dsb active (note 1) 2 ns ad[7:0], d[7:0] t10 output valid delay time from dsb inactive (note 1) 3 30 ns ackb t11 asserted delay from dsb active (note 1) 40 ns ackb t12 output delay time from dsb inactive (note 1) 12 ns asb t13 active delay time to dsb active (note 1) 10 ns note 1: the input/output timing reference level for all signals is v dd /2. note 2: in a nonmux cycle, the timing reference refers only to the dsb signal. while in a mux cycle, the timing reference refers only t o the asb signal.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 86 of 97 figure 10-5. motorola nonmux read cycle a[5:0] dsb csb d[7:0] ackb asb=(1) address data out t1 t6 t3 t10 t11 t 7 t2 t9 t12 rwb t8 t4 t5
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 87 of 97 figure 10-6. motorola mux read cycle dsb csb ad[7:0] ackb asb data out t1 t3 t10 t11 t2 t12 rwb t4 t5 address t13 t7 t8 t 9 t6
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 88 of 97 table 10-6. motorola write cycle characteristics (v dd = 3.3v 5%, tj = -40c to +125c.) ( figure 10-7 and figure 10-8 ) signal name(s) symbol description min typ max units dsb t1 pulse width (note 1) 60 ns csb t2 setup time to dsb active (note 1) 0 ns csb t3 hold time from dsb inactive (note 1) 0 ns rwb t4 setup time to dsb active (note 1) 10 ns rwb t5 hold time to dsb inactive (note 1) 0 ns ad[7:0] t6 setup time to asb/dsb active (notes 1, 2) 10 ns ad[7:0] t7 hold time from asb/dsb active (notes 1, 2) 5 ns ad[7:0], d[7:0] t8 setup time to dsb inactive (note 1) 40 ns ad[7:0], d[7:0] t9 hold time from dsb inactive (note 1) 30 ns a[5:0] t10 assert time from dsb active (note 1) 40 ns ackb t11 output delay from dsb inactive (note 1) 0 12 ns asb t12 active time to dsb active (note 1) 10 ns note 1: the input/output timing reference level for all signals is v dd /2. note 2: in a nonmux cycle, the timing reference refers only to the dsb signal. while in a mux cycle, the timing reference refers only t o the asb signal.
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 89 of 97 figure 10-7. motorola nonmux write cycle a[5:0] dsb csb d[7:0] ackb asb=(1) address write data t1 t 6 t3 t9 t10 t 7 t2 rwb t4 t5 t8 t 1 1
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 90 of 97 figure 10-8. motorola mux write cycle dsb csb ad[7:0] ackb address write data t1 t3 t9 t10 t2 rwb t4 t5 t 8 t11 asb t 7 t 6 t13 t12
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 91 of 97 10.3 serial port table 10-7. serial port timing characteristics ( figure 10-9 , figure 10-10 , and figure 10-11 ) parameter symbol conditions min typ max units sclk high time t1 25 ns sclk low time t2 25 ns active csb to sclk setup time t3 50 ns last sclk to csb inactive time t4 50 ns csb idle time t5 50 ns sdi to sclk setup time t6 5 ns sclk to sdi hold time t7 5 ns sclk falling edge to sdo high impedance (clke = 0); csb rising to sdo high impedance (clke = 1) t8 100 ns figure 10-9. serial bus timing write operation sclk sdi csb t3 t6 t4 t5 lsb msb t2 t1 t7 figure 10-10. serial bus timing read operation with clke = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk csb sd o t4 t8 figure 10-11. serial bus timing read operation with clke = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk csb sdo t4 t8
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 92 of 97 10.4 system timing table 10-8. transmitter system timing ( figure 10-12 ) parameter symbol conditions min typ max units tpos, tneg setup time with respect to tclk falling edge t1 40 ns tpos, tneg hold time with respect to tclk falling edge t2 40 ns tclk pulse-width high t3 75 ns tclk pulse-width low t4 75 ns 488 tclk period t5 648 ns tclk rise time t6 25 ns tclk fall time t7 25 ns figure 10-12. transmitter systems timing tpos, tneg t1 tclk t2 t3 t4 t5 t6 t7
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 93 of 97 table 10-9. receiver system timing ( figure 10-13 ) parameter symbol conditions min typ max units delay rclk to rpos, rneg valid t1 50 ns delay rclk to rneg valid in single- polarity mode t2 50 ns rclk pulse-width high t3 75 ns rclk pulse-width low t4 75 ns 488 rclk period t5 648 ns figure 10-13. receiver systems timing rneg rpos, rneg rpos, rneg bpv/ exz/ cv bpv/ exz/ cv t2 rclk 2 t5 t4 rclk 1 t3 t1 t1 bpv/ exz/ cv bpv/ exz/ cv rneg t2
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 94 of 97 10.5 jtag timing table 10-10. jtag timing characteristics ( figure 10-14 ) parameter symbol conditions min typ max units jtclk period t1 100 ns jtms and jtdi setup to jtclk t2 25 ns jtms and jtdi hold to jtclk t3 25 ns jtclk to jtdo hold t4 50 ns figure 10-14. jtag timing tck tms tdi tdo t1 t2 t3 t4
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 95 of 97 11 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallaspackinfo .) 11.1 elqfp package outline (1 of 2)
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 96 of 97 11.2 elqfp package outline (2 of 2)
ds26303: 3.3v, t1/e1/j1, short-haul, octal line interface unit 97 of 97 maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. 12 document revision history revision description 072205 new product release.

▲Up To Search▲

Price & Availability of DS26303LN-75

	To Download DS26303LN-75 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .